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2018-09-15x86: Set VexW=3 on AVX vrsqrtssH.J. Lu3-2/+7
2018-09-15x86: Set Vex=1 on VEX.128 only vmovqH.J. Lu4-6/+12
2018-09-14x86: Support VEX/EVEX WIG encodingH.J. Lu4-932/+941
2018-09-14x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit modeH.J. Lu3-2/+22
2018-09-14x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit modeH.J. Lu3-4/+23
2018-09-14i386: Reformat OP_E_memoryH.J. Lu2-2/+6
2018-09-14x86: fold CRC32 templatesJan Beulich3-45/+12
2018-09-13x86: Remove VexW=1 from WIG VEX movq and vmovqH.J. Lu2-8/+8
2018-09-13i386: Update VexW field for VEX instructionsH.J. Lu3-36/+44
2018-09-13x86: drop bogus IgnoreSize from a few further insnsJan Beulich3-52/+61
2018-09-13x86: drop bogus IgnoreSize from AVX512_4* insnsJan Beulich3-12/+18
2018-09-13x86: drop bogus IgnoreSize from AVX512DQ insnsJan Beulich3-96/+102
2018-09-13x86: drop bogus IgnoreSize from AVX512BW insnsJan Beulich3-78/+84
2018-09-13x86: drop bogus IgnoreSize from AVX512VL insnsJan Beulich3-26/+32
2018-09-13x86: drop bogus IgnoreSize from AVX512ER insnsJan Beulich3-32/+38
2018-09-13x86: drop bogus IgnoreSize from AVX512F insnsJan Beulich3-742/+748
2018-09-13x86: drop bogus IgnoreSize from SHA insnsJan Beulich3-16/+21
2018-09-13x86: drop bogus IgnoreSize from XOP and SSE4a insnsJan Beulich3-266/+271
2018-09-13x86: drop bogus IgnoreSize from AVX2 insnsJan Beulich3-238/+244
2018-09-13x86: drop bogus IgnoreSize from AVX insnsJan Beulich3-256/+262
2018-09-13x86: drop bogus IgnoreSize from GNFI insnsJan Beulich3-12/+17
2018-09-13x86: drop bogus IgnoreSize from PCLMUL/VPCLMUL insnsJan Beulich3-32/+37
2018-09-13x86: drop bogus IgnoreSize from AES/VAES insnsJan Beulich3-44/+49
2018-09-13x86: drop bogus IgnoreSize from SSE4.2 insnsJan Beulich3-20/+26
2018-09-13x86: drop bogus IgnoreSize from SSE4.1 insnsJan Beulich3-126/+132
2018-09-13x86: drop bogus IgnoreSize from SSSE3 insnsJan Beulich3-64/+70
2018-09-13x86: drop bogus IgnoreSize from SSE3 insnsJan Beulich3-36/+41
2018-09-13x86: drop bogus IgnoreSize from SSE2 insnsJan Beulich3-416/+421
2018-09-13x86: drop bogus IgnoreSize from SSE insnsJan Beulich3-118/+123
2018-09-13x86: drop unnecessary {,No}Rex64Jan Beulich3-10/+16
2018-09-13x86: also allow D on 3-operand insnsJan Beulich3-96/+18
2018-09-13x86: use D attribute also for SIMD templatesJan Beulich4-1277/+165
2018-09-13x86-64: bndmk, bndldx, and bndstx don't allow RIP-relative addressingJan Beulich2-3/+21
2018-09-08S12Z: Make disassebler work for --enable-targets=all config.John Darrington2-0/+5
2018-08-31RISC-V: Correct the requirement of compressed floating point instructionsJim Wilson2-16/+21
2018-08-30RISC-V: Allow instruction require more than one extensionJim Wilson3-630/+636
2018-08-29sparc/leon: add support for partial write psr instructionMartin Aberg2-0/+13
2018-08-29[MIPS] Add Loongson 2K1000 proccessor support.Chenghua Xu2-0/+9
2018-08-29[MIPS] Add Loongson 3A2000/3A3000 proccessor support.Chenghua Xu2-0/+9
2018-08-29[MIPS] Add Loongson 3A1000 proccessor support.Chenghua Xu3-2/+14
2018-08-29[MIPS/GAS] Add Loongson EXT2 Instructions support.Chenghua Xu3-0/+26
2018-08-29[MIPS/GAS] Split Loongson EXT Instructions from loongson3a.Chenghua Xu3-65/+88
2018-08-29[MIPS/GAS] Split Loongson CAM Instructions from loongson3aChenghua Xu3-6/+30
2018-08-21Use operand->extract to provide defaults for optional PowerPC operandsAlan Modra3-48/+82
2018-08-21Fix s12z test regexpsAlan Modra1-4/+3
2018-08-20Tidy bit twiddlingAlan Modra2-10/+12
2018-08-18Opcodes: (BRCLR / BRSET) Disassemble reserved codes instead of aborting.John Darrington2-20/+27
2018-08-18S12Z: Move opcode header to public include directory.John Darrington3-72/+5
2018-08-14x86-64: Display eiz for address with the addr32 prefixH.J. Lu2-7/+29
2018-08-11x86: Add CpuCMOV and CpuFXSRH.J. Lu6-7974/+8033
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