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2020-06-30RISC-V: Support debug and float CSR as the unprivileged ones.Nelson Chu2-3/+11
2020-06-29C++ commentsAlan Modra8-10/+19
2020-06-26i386-opc.tbl: Add a blank lineH.J. Lu2-0/+5
2020-06-26x86: Correct VexSIB128 to VecSIB128H.J. Lu2-29/+29
2020-06-26x86: Rename VecSIB to SIB for Intel AMXH.J. Lu4-85/+106
2020-06-26x86: make I disassembler macro available for new useJan Beulich2-13/+17
2020-06-26x86: fix processing of -M disassembler optionJan Beulich2-3/+8
2020-06-25x86: make J disassembler macro available for new useJan Beulich2-12/+13
2020-06-25x86: drop left-over 4-way alternative disassembler templatesJan Beulich2-2/+6
2020-06-25x86: fix SYSRET disassembly, improve {,V}CVTSI2S{S,D} and PTWRITEJan Beulich2-6/+14
2020-06-22RISC-V: Report warning when linking the objects with different priv specs.Nelson Chu3-50/+6
2020-06-18x86: also test alternative VMGEXIT encodingJan Beulich2-0/+6
2020-06-17x86: Delete incorrect vmgexit entry in prefix_tableCui,Lili2-2/+4
2020-06-14x86: Correct xsusldtrk mnemonicH.J. Lu4-3/+10
2020-06-12RISC-V: Drop the privileged spec v1.9 support.Nelson Chu2-1/+4
2020-06-11[PATCH]: aarch64: Refactor representation of system registersAlex Coplan2-623/+471
2020-06-09i386-dis.c: Fix a typo in commentsH.J. Lu2-1/+5
2020-06-09x86: consistently print prefixes explicitly which are invalid with VEX etcJan Beulich2-13/+11
2020-06-09x86: fix {,V}MOV{L,H}PD disassemblyJan Beulich2-23/+48
2020-06-09x86: utilize X macro in EVEX decodingJan Beulich6-411/+127
2020-06-09x86: correct decoding of packed-FP-only AVX encodingsJan Beulich2-31/+39
2020-06-09x86: correct mis-named MOD_0F51 enumeratorJan Beulich2-3/+8
2020-06-08[PATCH] arm: Add DFB instruction for ARMv8-RAlex Coplan2-0/+13
2020-06-08x86: restrict use of register aliasesJan Beulich2-1/+5
2020-06-06Power10 tidiesAlan Modra2-0/+9
2020-06-05bpf stack smashing detectedAlan Modra2-5/+11
2020-06-04cpu,gas,opcodes: remove no longer needed workaround from the BPF portJose E. Marchesi5-27/+35
2020-06-04opcodes: discriminate endianness and insn-endianness in CGEN portsJose E. Marchesi32-98/+145
2020-06-04opcodes: support insn endianness in cgen_cpu_openJose E. Marchesi30-70/+236
2020-06-03Updated Serbian translation for the opcodes sub-directoryNick Clifton2-530/+1480
2020-06-03RISC-V: Fix the error when building RISC-V linux native gdbserver.Nelson Chu2-8/+13
2020-06-01Regen opcodes/bpf-desc.cAlan Modra2-12/+8
2020-05-28cpu,opcodes: add instruction semantics to bpf.cpu and minor fixesJose E. Marchesi5-204/+243
2020-05-28ubsan: nios2: undefined shiftAlan Modra2-11/+10
2020-05-28asan: ns32k: use of uninitialized valueAlan Modra2-7/+8
2020-05-28Fix a potential use of an uninitialised value in the ns32k disassembler.Nick Clifton2-1/+9
2020-05-26Fix extraction of signed constants in nios2 disassembler (again).Sandra Loosemore2-8/+25
2020-05-26ChangeLog entries for f687f5f563Stefan Schulze Frielinghaus1-0/+6
2020-05-26S/390: z13: Accept vector alignment hintsStefan Schulze Frielinghaus1-12/+7
2020-05-21Replace "if (x) free (x)" with "free (x)", opcodesAlan Modra20-194/+88
2020-05-20[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...Nelson Chu4-63/+331
2020-05-19Power10 dcbf, sync, and wait extensions.Peter Bergner2-26/+243
2020-05-19or1k: Regenerate opcodes after removing 32-bit supportStafford Horne9-1648/+1195
2020-05-11Power10 VSX scalar min-max-compare quad precision operationsAlan Modra2-0/+16
2020-05-11Power10 VSX load/store rightmost element operationsAlan Modra2-0/+21
2020-05-11Power10 test lsb by byte operationAlan Modra2-0/+5
2020-05-11Power10 string operationsAlan Modra2-0/+15
2020-05-11Power10 Set boolean extensionPeter Bergner2-0/+13
2020-05-11Power10 bit manipulation operationsAlan Modra2-1/+27
2020-05-11Power10 VSX PCV generate operationsAlan Modra2-0/+9
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