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2023-08-26Simplify definition of GUILETom Tromey4-4/+8
This patch sets GUILE to just plain 'guile'. In the distant ("devo") past, the top-level build did support building Guile in-tree. However, I don't think this really works any more. For one thing, there are no build dependencies on it, so there's no guarantee it would actually be built before the uses. This patch also removes the use of "-s" as an option to cgen scheme scripts. With my latest patch upstream, this is no longer needed. After the upstream changes, either Guile 2 or Guile 3 will work, with or without the compiler enabled. 2023-08-24 Tom Tromey <tom@tromey.com> * cgen.sh: Don't pass "-s" to cgen. * Makefile.in: Rebuild. * Makefile.am (GUILE): Simplify.
2023-08-26opcodes i386 and ia64 gen file warningsAlan Modra2-3/+5
i386: warning: format ‘%u’ expects argument of type ‘unsigned int’, but argument 4 has type ‘size_t’ {aka ‘long unsigned int’} [-Wformat=] ia64: warning: ignoring return value of ‘fgets’ * i386-gen.c (process_i386_opcodes): Correct format string. * ia64-gen.c (load_insn_classes, load_depfile): Don't ignore fgets return value.
2023-08-24kvx: fix kvx_reassemble_bundle index 8 out of boundsPaul Iannetta1-2/+2
opcodes/ * kvx-dis.c (print_insn_kvx): Change the loop condition so that wordcount is always less than KVXMAXBUNDLEWORDS. (decode_prologue_epilogue_bundle): Likewise.
2023-08-24kvx: workaround gcc-4.5 bugAlan Modra1-2/+4
kvx-dis.c:1078:10: error: missing initializer kvx-dis.c:1078:10: error: (near initialization for 'dec.nb_ops') * kvx-dis.c (print_insn_kvx): Init dec with memset. (decode_prologue_epilogue_bundle): Likewise.
2023-08-24kvx: use {u,}int32_t and {u,}int64_tPaul Iannetta2-17/+17
gas/ * config/kvx-parse.c (promote_token): Use {u,}int32_t and {u,}int64_t. (get_token_class): Likewise. * config/tc-kvx.c (insert_operand): Likewise. * config/tc-kvx.h (struct token_s): Likewise. (struct token_list): Likewise. opcodes/ * kvx-dis.c (struct decoded_insn): Use {u,}int32_t and {u,}int64_t. (decode_insn): Likewise. (print_insn_kvx): Likewise. (decode_prologue_epilogue_bundle): Likewise. * kvx-dis.h (struct kvx_prologue_epilogue_insn): Likewise.
2023-08-22aarch64: Improve naming conventions for A and R-profile architectureVictor Do Nascimento3-219/+219
Historically, flags and variables relating to architectural revisions for the A-profile architecture omitted the trailing `A' such that, for example, assembling for `-march=armv8.4-a' set the `AARCH64_ARCH_V8_4' flag in the assembler. This leads to some ambiguity, since Binutils also targets the R-profile Arm architecture. Therefore, it seems prudent to have everything associated with the A-profile cores end in `A' and likewise `R' for the R-profile. Referring back to the example above, the flag set for `-march=armv8.4-a' is better characterized if labeled `AARCH64_ARCH_V8_4A'. The only exception to the rule of appending `A' to variables is found in the handling of the `AARCH64_FEATURE_V8' macro, as it is the baseline from which ALL processors derive and should therefore be left unchanged. In reflecting the `ARM' architectural nomenclature choices, where we have `ARM_ARCH_V8A' and `ARM_ARCH_V8R', the choice is made to not have an underscore separating the numerical revision number and the A/R-profile indicator suffix. This has meant that renaming of R-profile related flags and variables was warranted, thus going from `.*_[vV]8_[rR]' to `.*_[vV]8[rR]'. Finally, this is more in line with conventions within GCC and adds consistency across the toolchain. gas/ChangeLog: * gas/config/tc-aarch64.c: (aarch64_cpus): Reference to arch feature macros updated. (aarch64_archs): Likewise. include/ChangeLog: * include/opcode/aarch64.h: (AARCH64_FEATURE_V8A): Updated name: V8_A -> V8A. (AARCH64_FEATURE_V8_1A): A-suffix added. (AARCH64_FEATURE_V8_2A): Likewise. (AARCH64_FEATURE_V8_3A): Likewise. (AARCH64_FEATURE_V8_4A): Likewise. (AARCH64_FEATURE_V8_5A): Likewise. (AARCH64_FEATURE_V8_6A): Likewise. (AARCH64_FEATURE_V8_7A): Likewise. (AARCH64_FEATURE_V8_8A):Likewise. (AARCH64_FEATURE_V9A): Likewise. (AARCH64_FEATURE_V8R): Updated name: V8_R -> V8R. (AARCH64_ARCH_V8A_FEATURES): Updated name: V8_A -> V8A. (AARCH64_ARCH_V8_1A_FEATURES): A-suffix added. (AARCH64_ARCH_V8_2A_FEATURES): Likewise. (AARCH64_ARCH_V8_3A_FEATURES): Likewise. (AARCH64_ARCH_V8_4A_FEATURES): Likewise. (AARCH64_ARCH_V8_5A_FEATURES): Likewise. (AARCH64_ARCH_V8_6A_FEATURES): Likewise. (AARCH64_ARCH_V8_7A_FEATURES): Likewise. (AARCH64_ARCH_V8_8A_FEATURES): Likewise. (AARCH64_ARCH_V9A_FEATURES): Likewise. (AARCH64_ARCH_V9_1A_FEATURES): Likewise. (AARCH64_ARCH_V9_2A_FEATURES): Likewise. (AARCH64_ARCH_V9_3A_FEATURES): Likewise. (AARCH64_ARCH_V8A): Updated name: V8_A -> V8A. (AARCH64_ARCH_V8_1A): A-suffix added. (AARCH64_ARCH_V8_2A): Likewise. (AARCH64_ARCH_V8_3A): Likewise. (AARCH64_ARCH_V8_4A): Likewise. (AARCH64_ARCH_V8_5A): Likewise. (AARCH64_ARCH_V8_6A): Likewise. (AARCH64_ARCH_V8_7A): Likewise. (AARCH64_ARCH_V8_8A): Likewise. (AARCH64_ARCH_V9A): Likewise. (AARCH64_ARCH_V9_1A): Likewise. (AARCH64_ARCH_V9_2A): Likewise. (AARCH64_ARCH_V9_3A): Likewise. (AARCH64_ARCH_V8_R): Updated name: V8_R -> V8R. opcodes/ChangeLog: * opcodes/aarch64-opc.c (SR_V8A): Updated name: V8_A -> V8A. (SR_V8_1A): A-suffix added. (SR_V8_2A): Likewise. (SR_V8_3A): Likewise. (SR_V8_4A): Likewise. (SR_V8_6A): Likewise. (SR_V8_7A): Likewise. (SR_V8_8A): Likewise. (aarch64_sys_regs): Reference to arch feature macros updated. (aarch64_pstatefields): Reference to arch feature macros updated. (aarch64_sys_ins_reg_supported_p): Reference to arch feature macros updated. * opcodes/aarch64-tbl.h: (aarch64_feature_v8_2a): a-suffix added. (aarch64_feature_v8_3a): Likewise. (aarch64_feature_fp_v8_3a): Likewise. (aarch64_feature_v8_4a): Likewise. (aarch64_feature_fp_16_v8_2a): Likewise. (aarch64_feature_v8_5a): Likewise. (aarch64_feature_v8_6a): Likewise. (aarch64_feature_v8_7a): Likewise. (aarch64_feature_v8r): Updated name: v8_r-> v8r. (ARMV8R): Updated name: V8_R-> V8R. (ARMV8_2A): A-suffix added. (ARMV8_3A): Likewise. (FP_V8_3A): Likewise. (ARMV8_4A): Likewise. (FP_F16_V8_2A): Likewise. (ARMV8_5): Likewise. (ARMV8_6A): Likewise. (ARMV8_6A_SVE): Likewise. (ARMV8_7A): Likewise. (V8_2A_INSN): `A' added to macro symbol. (V8_3A_INSN): Likewise. (V8_4A_INSN): Likewise. (FP16_V8_2A_INSN): Likewise. (V8_5A_INSN): Likewise. (V8_6A_INSN): Likewise. (V8_7A_INSN): Likewise. (V8R_INSN): Updated name: V8_R-> V8R.
2023-08-22kvx_dis_initAlan Modra1-20/+3
kvx_dis_init currently always returns true, but error conditions do so by "return -1" which converts to true. The return status is ignored anyway, and it doesn't make much sense to error on unexpected arch or mach: If print_insn_kvx is called then the atch is known to be kvx, and it's better to choose some default for a user passing an unknown mach value rather than segfaulting in decode_insn when env.opc_table is NULL. I've chosen the default mach to be bfd_mach_kv3_1, the default in bfd/cpu-kvx.c, not that it matters very much. In normal objdump/gdb usage, info->mach won't be an unexpected value. * kvx-dis.c (kvx_dis_init): Return void. Don't error on unexpected arch or mach. Default to bfd_mach_kv3_1 for unknown mach. Don't clear info->disassembler_options.
2023-08-21bpf: correct neg and neg32 instruction encodingDavid Faust1-4/+0
The neg/neg32 BPF instructions always use BPF_SRC_K (=0) in their header source bit, despite operating on registers. If BPF_SRC_X (=1) is set, the instructions are rejected by the kernel. Because of this there are also no neg/neg32 instructions which operate on immediates, so remove them. bd434cc4d94ec3d2f9fc1e7c00c27b074f962bc1 was a similar fix in the old CGEN-based port, but was not carried forward in the new port. include/ * opcode/bpf.h (enum bpf_insn_id): Remove spurious entries BPF_INSN_NEGI and BPF_INSN_NEG32I. opcodes/ * bpf-opc.c (bpf_opcodes): Remove erroneous NEGI and NEG32I instructions. gas/ * doc/c-bpf.texi (BPF Instructions): Remove erroneous neg and neg32 instructions operating on immediates. * testsuite/gas/bpf/alu.s: Adapt accordingly. * testsuite/gas/bpf/alu.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise * testsuite/gas/bpf/alu32.s: Likewise. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
2023-08-19sim --enable-cgen-maintAlan Modra2-2/+8
I had reason yesterday to want to regenerate configury files which I do with --enable-maintainer-mode, and added --enable-cgen-maint accidentally. The first problem I hit is that sim looks for cgen in a different directory by default than opcodes, and I had my source layout set up for opcodes rather than sim. Fix that by making both use ../cgen first, then ../../cgen relative to sim/ and opcodes/. The next problem was that various sim local.mk files expected generated sources in the build dir rather than the source dir. Fix that by adding $(srcdir) to paths. Finally, the generated iq2000 files had a compile error, fixed by the cpu/iq2000.cpu patch. cpu/ * iq2000.cpu (syscall): Add pc arg. opcodes/ * configure.ac (cgendir): Default to ../../cgen, but use ../cgen if found there. * configure: Regenerate. sim/m4/ * sim_ac_option_cgen_maint.m4 (cgendir): Look in ../cgen too. sim/ * cris/local.mk: Add $(srcdir) to paths for regenerated source. * frv/local.mk: Likewise. * iq2000/local.mk: Likewise. * lm32/local.mk: Likewise. * m32r/local.mk: Likewise. * or1k/local.mk: Likewise. * Makefile.in: Regenerate. * configure: Regenerate.
2023-08-16kvx: New port.Paul Iannetta10-0/+112808
2023-08-15RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa'Tsukasa OI1-1/+1
The documentation of the 'Zfa' extension states that "fli.h" is available "if the Zfh or Zvfh extension is implemented" (both the latest and the oldest editions are checked). This fact was not reflected in Binutils ('Zvfh' implies 'Zfhmin', not full 'Zfh' extension and "fli.h" required 'Zfh' and 'Zfa' extensions). This commit makes "fli.h" also available when both 'Zfa' and 'Zvfh' extensions are implemented. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add new instruction class handling. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zfa-zvfh.s: New test. * testsuite/gas/riscv/zfa-zvfh.d: Ditto. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Add new instruction class. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Change instruction class of "fli.h" from INSN_CLASS_ZFH_AND_ZFA to new INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA.
2023-08-15RISC-V: Add support for the 'Zihintntl' extensionTsukasa OI1-0/+12
This commit adds 'Zihintntl' extension and its hint instructions. This is based on: <https://github.com/riscv/riscv-isa-manual/commit/0dc91f505e6da7791d5a733c553e6e2506ddcab5>, the first ISA Manual noting that the 'Zihintntl' extension is ratified. Note that compressed 'Zihintntl' hints require either 'C' or 'Zca' extension. Co-authored-by: Nelson Chu <nelson@rivosinc.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_z_ext): Add 'Zihintntl' standard hint 'Z' extension. (riscv_multi_subset_supports): Support new instruction classes. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zihintntl.s: New test for 'Zihintntl' including auto-compression without C prefix and explicit C prefix. * testsuite/gas/riscv/zihintntl.d: Likewise. * testsuite/gas/riscv/zihintntl-na.d: Likewise. * testsuite/gas/riscv/zihintntl-base.s: New test for correspondence between 'Zihintntl' and base 'I' or 'C' instructions. * testsuite/gas/riscv/zihintntl-base.d: Likewise. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): Add new instruction classes: INSN_CLASS_ZIHINTNTL and INSN_CLASS_ZIHINTNTL_AND_C. (MASK_NTL_P1, MATCH_NTL_P1, MASK_NTL_PALL, MATCH_NTL_PALL, MASK_NTL_S1, MATCH_NTL_S1, MASK_NTL_ALL, MATCH_NTL_ALL, MASK_C_NTL_P1, MATCH_C_NTL_P1, MASK_C_NTL_PALL, MATCH_C_NTL_PALL, MASK_C_NTL_S1, MATCH_C_NTL_S1, MASK_C_NTL_ALL, MATCH_C_NTL_ALL): New. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add instructions from the 'Zihintntl' extension.
2023-08-15RISC-V: remove indirection from register tablesJan Beulich2-12/+12
The longest register name is 4 characters (plus a nul one), so using a 4- or 8-byte pointer to get at it is neither space nor time efficient. Embed the names right into the array. For PIE this also reduces the number of base relocations in the final image. To avoid old gcc, when generating 32-bit code, bogusly warning about bounds being exceeded in the code processing Cs/Cw, Ct/Cx, and CD, an adjustment to EXTRACT_BITS() is needed: This macro shouldn't supply a 64-bit value, and it also doesn't need to - all operand fields to date are far more narrow than 32 bits. This in turn allows dropping a number of casts elsewhere.
2023-08-12regen configAlan Modra1-21/+52
This regenerates config files changed by the previous 44 commits. Note that subject lines in these commits mostly match the gcc git originating commit.
2023-08-11x86: pack CPU flags in opcode tableJan Beulich4-31432/+4568
The table constantly growing in two dimensions (number of table entries times number of ISA extension flags) doesn't scale very well. Use a more compact representation: Only identifiers which need to combine with other identifiers retain individual flag bits. All others are combined into an enum, with a new helper added to transform the table entries into the original i386_cpu_flags layout. This way the table in the final binary shrinks by almost a third (the generated source code shrinks by about half), and isn't likely to grow again in that dimension any time soon. While moving the 3DNow! fields, drop the stray inner 'a' from their names.
2023-08-11RISC-V: Fix opcode entries of "vmsge{,u}.vx"Tsukasa OI1-4/+4
Their check_func should be "match_never", not "match_opcode". The reasons this error did not cause any disassembler errors are: 1. The problem will not reproduce if "no-aliases" is specified (because macro instructions are handled as aliases). 2. If not, all affected compressed instructions or their aliases precede before "vmsge{,u}.vx" macro instructions. However, it'll easily break if we reorder opcode entries. This commit fixes this issue before the *accident* occurs. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Make sure that we never match to vmsge{,u}.vx instructions unless specified in the assembler.
2023-08-09bpf: use w regs in 32-bit non-fetch atomic pseudo-cDavid Faust1-4/+4
The 32-bit non-fetching atomic instructions treat the source register as 32-bits, which means in the pseudo-c syntax the "w" registers should be used rather than the "r" registers. opcodes/ * bpf-opc-c (bpf_opcodes): Use %sw for AAD32, AOR32, AAND32 and AXOR32 pseudo-c dialect asm templates. gas/ * testsuite/gas/bpf/atomic-be-pseudoc.d: Use "w" for source reg in non-fetching 32-bit atomic instructions. * testsuite/gas/bpf/atomic-pseudoc.d: Likewise. * testsuite/gas/bpf/atomic-pseudoc.s: Likewise.
2023-08-07RISC-V: move comment describing rules for riscv_opcodes[]Jan Beulich1-10/+10
It makes little sense to have this comment meanwhile over a hundred lines ahead of the array. In fact until spotting the comment, I was wondering why those pretty important aspects aren't spelled out anywhere.
2023-08-03cris: sprintf optimisationAlan Modra1-19/+10
Since I was poking at cris-dis.c to avoid the sanitizer warning, I figure I might as well make use of stpcpy and sprintf return value in other places in this file. * cris-dis.c (format_hex): Use sprintf return value. (format_reg): Use stpcpy and sprintf return, avoiding strlen. (format_sup_reg): Likewise.
2023-08-03cris: sprintf sanitizer null destination pointerAlan Modra1-6/+1
Simplify the sprintf calls, and use sprintf return value. Older code in binutils avoided using the sprintf return count of chars printed, because with some older C libraries it wasn't reliable. Nowadays it should be OK to use (and we already use the return value elsewhere). sprintf can't return an error status of -1 here. * cris-dis.c (format_dec): Avoid sanitizer warning. Use sprintf return value rather than calling strlen.
2023-08-03 Fix Wlto-type-mismatch in opcodes/ft32-dis.cTom de Vries1-1/+1
2023-08-02Revert "2.41 Release sources"Sam James26-10922/+13254
This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton26-13254/+10922
2023-07-31bpf: opcodes: fix regression in BPF disassemblerJose E. Marchesi2-1/+7
This patch fixes a regression recently introduced in the BPF disassembler, that was assuming an abfd was always available in info->section->owner. Apparently this is not so in GDB, and therefore https://sourceware.org/bugzilla/show_bug.cgi?id=30705. Tested in bpf-unkonwn-none. opcodes/ChangeLog: 2023-07-31 Jose E. Marchesi <jose.marchesi@oracle.com> PR 30705 * bpf-dis.c (print_insn_bpf): Check that info->section->owner is actually available before using it.
2023-07-30bpf: include, bfd, opcodes: add EF_BPF_CPUVER ELF header flagsJose E. Marchesi3-21/+36
This patch adds support for EF_BPF_CPUVER bits in the ELF machine-dependent header flags. These bits encode the BPF CPU version for which the object file has been compiled for. The BPF assembler is updated so it annotates the object files it generates with these bits. The BPF disassembler is updated so it honors EF_BPF_CPUVER to use the appropriate ISA version if the user didn't specify an explicit ISA version in the command line. Note that a value of zero in EF_BPF_CPUVER is interpreted by the disassembler as "use the later supported version" (the BPF CPU versions start with v1.) The readelf utility is updated to pretty print EF_BPF_CPUVER when it prints out the ELF header: $ readelf -h a.out ELF Header: ... Flags: 0x4, CPU Version: 4 Tested in bpf-unknown-none. include/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * elf/bpf.h (EF_BPF_CPUVER): Define. * opcode/bpf.h (BPF_XBPF): Change from 0xf to 0xff so it fits in EF_BPF_CPUVER. binutils/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * readelf.c (get_machine_flags): Recognize and pretty print BPF machine flags. opcodes/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-dis.c: Initialize asm_bpf_version to -1. (print_insn_bpf): Set BPF ISA version from the cpu version ELF header flags if no explicit version set in the command line. * disassemble.c (disassemble_init_for_target): Remove unused code. gas/ChangeLog: 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.h (elf_tc_final_processing): Define. * config/tc-bpf.c (bpf_elf_final_processing): New function.
2023-07-28Fix typo in riscv-dis.c commentTsukasa OI1-1/+1
Don't go "past" the start of the section.
2023-07-27Support Intel PBNDKBHu, Lin17-6040/+6090
gas/ChangeLog: * NEWS: Support Intel PBNDKB. * config/tc-i386.c: Add pbndkb. * doc/c-i386.texi: Document .pbndkb. * testsuite/gas/i386/i386.exp: Add PBNDKB tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/pbndkb-inval.l: New test. * testsuite/gas/i386/pbndkb-inval.s: Ditto. * testsuite/gas/i386/x86-64-pbndkb-intel.d: Ditto. * testsuite/gas/i386/x86-64-pbndkb.d: Ditto. * testsuite/gas/i386/x86-64-pbndkb.s: Ditto. opcodes/ChangeLog: * i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_7): New. (X86_64_0F01_REG_0_MOD_3_RM_7_P_0): Ditto. (prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_7. (x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_7_P_0. (rm_table): New entry for pbndkb. * i386-gen.c (cpu_flag): Add PBNDKB. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuPBNDKB): New. (i386_cpu_flags): Add cpupbndkb. * i386-opc.tbl: Add PBNDKB instructions. * i386-tbl.h: Regenerated.
2023-07-27Support Intel SM4Haochen Jiang7-6751/+6825
gas/ChangeLog: * NEWS: Support Intel SM4. * config/tc-i386.c: Add sm4. * doc/c-i386.texi: Document .sm4. * testsuite/gas/i386/i386.exp: Run SM4 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/sm4-intel.d: Add SM4 tests. * testsuite/gas/i386/sm4.d: Ditto. * testsuite/gas/i386/sm4.s: Ditto. * testsuite/gas/i386/x86-64-sm4-intel.d: Ditto. * testsuite/gas/i386/x86-64-sm4.d: Ditto. * testsuite/gas/i386/x86-64-sm4.s: Ditto. opcodes/ChangeLog: * i386-dis.c (prefix_table): Add SM4 instructions. * i386-gen.c (isa_dependencies): Add SM4. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuSM4): New. (i386_cpu_flags): Add cpusm4. * i386-opc.tbl: Add SM4 instructions. * i386-tbl.h: Regenerated.
2023-07-27Support Intel SM3Haochen Jiang7-6974/+7105
gas/ChangeLog: * NEWS: Support Intel SM3. * config/tc-i386.c: Add sm3. * doc/c-i386.texi: Document .sm3. * testsuite/gas/i386/i386.exp: Run sm3 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/sm3-intel.d: New test. * testsuite/gas/i386/sm3.d: Ditto. * testsuite/gas/i386/sm3.s: Ditto. * testsuite/gas/i386/x86-64-sm3-intel.d: Ditto. * testsuite/gas/i386/x86-64-sm3.d: Ditto. * testsuite/gas/i386/x86-64-sm3.s: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_VEX_0F38DA_W_0): New. (VEX_LEN_0F38DA_W_0_P_0): Ditto. (VEX_LEN_0F38DA_W_0_P_2): Ditto. (VEX_LEN_0F3ADE_W_0): Ditto. (VEX_W_0F38DA): Ditto. (VEX_W_0F3ADE): Ditto. (prefix_table): Add PREFIX_VEX_0F38DA_W_0. (vex_len_table): Add VEX_LEN_0F38DA_W_0_P_0, VEX_LEN_0F38DA_W_0_P_2, VEX_LEN_0F3ADE_W_0. (vex_w_table): Add VEX_W_0F38DA, VEX_W_0F3ADE. * i386-gen.c (isa_dependencies): Add SM3. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuSM3): New. (i386_cpu_flags): Add cpusm3. * i386-opc.tbl: Add SM3 instructions. * i386-tbl.h: Regenerated.
2023-07-27Support Intel SHA512Haochen Jiang7-7051/+7206
gas/ChangeLog: * NEWS: Support Intel SHA512. * config/tc-i386.c: Add sha512. * doc/c-i386.texi: Document .sha512. * testsuite/gas/i386/disassem.d: Add SHA512 tests. * testsuite/gas/i386/disassem.s: Ditto. * testsuite/gas/i386/i386.exp: Run SHA512 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/sha512-intel.d: New test. * testsuite/gas/i386/sha512-inval.l: Ditto. * testsuite/gas/i386/sha512-inval.s: Ditto. * testsuite/gas/i386/sha512.d: Ditto. * testsuite/gas/i386/sha512.s: Ditto. * testsuite/gas/i386/x86-64-sha512-intel.d: Ditto. * testsuite/gas/i386/x86-64-sha512-inval.l: Ditto. * testsuite/gas/i386/x86-64-sha512-inval.s: Ditto. * testsuite/gas/i386/x86-64-sha512.d: Ditto. * testsuite/gas/i386/x86-64-sha512.s: Ditto. opcodes/ChangeLog: * i386-dis.c (Rxmmq): New. (Rymm): Ditto. (PREFIX_VEX_0F38CB): Ditto. (PREFIX_VEX_0F38CC): Ditto. (PREFIX_VEX_0F38CD): Ditto. (VEX_LEN_0F38CB_P_3_W_0): Ditto. (VEX_LEN_0F38CC_P_3_W_0): Ditto. (VEX_LEN_0F38CD_P_3_W_0): Ditto. (VEX_W_0F38CB_P_3): Ditto. (VEX_W_0F38CC_P_3): Ditto. (VEX_W_0F38CD_P_3): Ditto. (prefix_table): Add PREFIX_VEX_0F38CB, PREFIX_VEX_0F38CC, PREFIX_VEX_0F38CD. (vex_len_table): Add VEX_LEN_0F38CB_P_3_W_0, VEX_LEN_0F38CC_P_3_W_0, VEX_LEN_0F38CD_P_3_W_0. (vex_w_table): Add VEX_W_0F38CB_P_3, VEX_W_0F38CC_P_3, VEX_W_0F38CD_P_3. * i386-gen.c (isa_dependencies): Add SHA512. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuSHA512): New. (i386_cpu_flags): Add cpusha512. * i386-opc.tbl: Add SHA512 instructions. * i386-tbl.h: Regenerated.
2023-07-27Support Intel AVX-VNNI-INT16konglin17-5622/+9878
gas/ChangeLog: * NEWS: Support Intel AVX-VNNI-INT16. * config/tc-i386.c: Add avx_vnni_int16. * doc/c-i386.texi: Document avx_vnni_int16. * testsuite/gas/i386/i386.exp: Run AVX VNNI INT16 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx-vnni-int16-intel.d: New test. * testsuite/gas/i386/avx-vnni-int16.d: New test. * testsuite/gas/i386/avx-vnni-int16.s: New test. * testsuite/gas/i386/x86-64-avx-vnni-int16-intel.d: New test. * testsuite/gas/i386/x86-64-avx-vnni-int16.d: New test. * testsuite/gas/i386/x86-64-avx-vnni-int16.s: New test. opcodes/ChangeLog: * i386-dis.c (PREFIX_VEX_0F38D2_W_0): New. (PREFIX_VEX_0F38D3_W_0): Ditto. (VEX_W_0F38D2_P_0): Ditto. (VEX_W_0F38D2_P_1): Ditto. (VEX_W_0F38D2_P_2): Ditto. (VEX_W_0F38D3_P_0): Ditto. (VEX_W_0F38D3_P_1): Ditto. (VEX_W_0F38D3_P_2): Ditto. (prefix_table): Add PREFIX_VEX_0F38D2_W_0 and PREFIX_VEX_0F38D3_W_0. (vex_table): Add VEX_W_0F38D2 and VEX_W_0F38D3. (vex_w_table): Ditto. * i386-gen.c (isa_dependencies): Add AVX_VNNI_INT16. (cpu_flag): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h: (CpuAVX_VNNI_INT16): New. * i386-opc.tbl: Add Intel AVX_VNNI_INT16 instructions. * i386-tbl.h: Regenerated.
2023-07-26bpf: fix register NEG[32] instructionsJose E. Marchesi2-2/+7
This patch fixes the BPF_INSN_NEGR and BPF_INSN_NEG32R BPF instructions to not use their source registers. Tested in bpf-unknown-none. opcodes/ChangeLog: 2023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Fix BPF_INSN_NEGR to not use a src register. gas/ChangeLog: 2023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.s: The register neg instruction gets only one argument. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu32.s: Likewise. * doc/c-bpf.texi (BPF Instructions): Update accordingly.
2023-07-26Regen bpf opcodes POTFILEAlan Modra3-7/+2
2023-07-25bpf: Add atomic compare-and-exchange instructionsDavid Faust1-0/+12
This patch adds the two remaining BPF v3 atomic instructions: - BPF_INSN_ACMP{,32}: atomic compare-and-swap - BPF_INSN_AXCHG{,32}: atomic (non-conditional) exchange Tests and documentation are also updated. gas/ * doc/c-bpf.texi (BPF Instructions): Document atomic exchange and atomic compare-and-swap instructions. * testsuite/gas/bpf/atomic.s: Test ACMP, ACMP32, AXCHG, AXCGH32 instructions. * testsuite/gas/bpf/atomic.d: Likewise. * testsuite/gas/bpf/atomic-be.d: Likewise. * testsuite/gas/bpf/atomic-pseudoc.s: Likewise. * testsuite/gas/bpf/atomic-pseudoc.d: Likewise. * testsuite/gas/bpf/atomic-be-pseudoc.d: Likewise. include/ * opcode/bpf.h (BPF_IMM32_ACMP): Fix typo. (enum bpf_insn_id): New entries for BPF_INSN_ACMP{,32} and BPF_INSN_AXCHG{,32}. opcodes/ * bpf-opc.c (bpf_opcodes): Add entries for ACMP{,32} and AXCHG{,32} instructions.
2023-07-25bpf: Update atomic instruction pseudo-C syntaxDavid Faust1-16/+16
This patch updates the pseudo-C dialect templates for the BPF v3 atomic instructions. The templates match the strings emitted by clang -S for these instructions. The tests and documentation are updated accordingly. gas/ * doc/c-bpf.texi (BPF Instructions): Update entries for atomic and 32-bit atomic instructions. * testsuite/gas/bpf/atomic.s: Test AAND, AAND32, AOR, AOR32, AXOR, AXOR32, AFADD, AFADD32, AFAND, AFAND32, AFOR, AFOR32, AFXOR and AFXOR32 instructions. * testsuite/gas/bpf/atomic.d: Likewise. * testsuite/gas/bpf/atomic-be.d: Likewise. * testsuite/gas/bpf/atomic-pseudoc.s: Likewise. * testsuite/gas/bpf/atomic-pseudoc.d: Likewise. * testsuite/gas/bpf/atomic-be-pseudoc.d: Likewise. * testsuite/gas/bpf/atomic-v1.s: New test. * testsuite/gas/bpf/atomic-v1.d: Likewise. * testuiste/gas/bpf/atomic-v1-be.d: Likewise. * testuiste/gas/bpf/bpf.exp: Run new tests. opcodes/ * bpf-opc.c (bpf_opcodes): Update pseudo-C dialect templates for: BPF_INSN_AADD, BPF_INSN_AOR, BPF_INSN_AAND, BPF_INSN_AXOR, BPF_INSN_AFADD, BPF_INSN_AFOR, BPF_INSN_AFAND, BPF_INSN_AFXOR, BPF_INSN_AADD32, BPF_INSN_AOR32, BPF_INSN_AAND32, BPF_INSN_AXOR32, BPF_INSN_AFADD32, BPF_INSN_AFOR32, BPF_INSN_AFAND32, and BPF_INSN_AFXOR32 instructions.
2023-07-24Updated translations for bfd, gold and opcodesNick Clifton1-372/+341
2023-07-24bpf: gas,include,opcode: add suppor for instructions BSWAP{16,32,64}Jose E. Marchesi2-0/+13
This patch adds support for the BPF V4 ISA byte swap instructions to opcodes, assembler and disassembler. Tested in bpf-unknown-none. include/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (BPF_IMM32_BSWAP16): Define. (BPF_IMM32_BSWAP32): Likewise. (BPF_IMM32_BSWAP64): Likewise. (enum bpf_insn_id): New entries BPF_INSN_BSWAP{16,32,64}. opcodes/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entries for the BSWAP* instructions. gas/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-bpf.texi (BPF Instructions): Document BSWAP* instructions. * testsuite/gas/bpf/alu.s: Test BSWAP{16,32,64} instructions. * testsuite/gas/bpf/alu.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
2023-07-24bpf: gas,opcodes: fix pseudoc syntax for MOVS* and LDXS* insnsJose E. Marchesi2-10/+15
This patch fixes the pseudoc syntax of the V4 instructions MOVS* and LDXS* in order to reflect https://reviews.llvm.org/D144829. opcodes/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Fix pseudo-c syntax for MOVS* and LDXS* instructions. gas/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-bpf.texi (BPF Instructions): Fix pseudoc syntax for MOVS* and LDXS* instructions. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-be-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
2023-07-24bpf: add support for jal/gotol jump instruction with 32-bit targetJose E. Marchesi2-0/+8
This patch adds support for the V4 BPF instruction jal/gotol, which is like ja/goto but it supports a signed 32-bit PC-relative (in number of 64-bit words minus one) target operand instead of the 16-bit signed operand of the other instruction. This greatly increases the jump range in BPF programs. Tested in bpf-unkown-none. bfd/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * reloc.c: New reloc BFD_RELOC_BPF_DISPCALL32. * elf64-bpf.c (bpf_reloc_type_lookup): Handle the new reloc. * libbfd.h (bfd_reloc_code_real_names): Regenerate. gas/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-bpf.c (struct bpf_insn): New field `id'. (md_assemble): Save the ids of successfully parsed instructions and use the new BFD_RELOC_BPF_DISPCALL32 whenever appropriate. (md_apply_fix): Adapt to the new BFD reloc. * testsuite/gas/bpf/jump.s: Test JAL. * testsuite/gas/bpf/jump.d: Likewise. * testsuite/gas/bpf/jump-pseudoc.d: Likewise. * testsuite/gas/bpf/jump-be.d: Likewise. * testsuite/gas/bpf/jump-be-pseudoc.d: Likewise. * doc/c-bpf.texi (BPF Instructions): Document new instruction jal/gotol. Document new operand type disp32. include/ChangeLog: 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (enum bpf_insn_id): Add entry BPF_INSN_JAL. (enum bpf_insn_id): Remove spurious entry BPF_INSN_CALLI. opcodes/ChangeLog: 2023-07-23 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entry for jal.
2023-07-21bpf: disasemble offsets of value 0 as "+0"David Faust1-2/+2
This tiny patch makes the BPF disassembler to emit, e.g. ldxdw %r1, [%r0+0] instead of ldxdw %r1, [%r00] when the offset is 0, to avoid confusion. opcodes/ * bpf-dis.c (print_insn_bpf): Print offsets with value 0 as "+0". gas/ * testsuite/gas/bpf/mem.s: Add tests with offset 0. * testsuite/gas/bpf/mem-pseudoc.s: Likewise. * testsuite/gas/bpf/mem.d: Update accordingly. * testsuite/gas/bpf/mem-be.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-be-pseudoc.d: Likewise.
2023-07-21bpf: opcodes, gas: support for signed load V4 instructionsJose E. Marchesi2-0/+15
This commit adds the signed load to register (ldxs*) instructions introduced in the BPF ISA version 4, including opcodes and assembler tests. Tested in bpf-unknown-none. include/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (enum bpf_insn_id): Add entries for signed load instructions. (BPF_MODE_SMEM): Define. opcodes/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW} instructions. gas/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/mem.s: Add signed load instructions. * testsuite/gas/bpf/mem-pseudoc.s: Likewise. * testsuite/gas/bpf/mem.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-be.d: Likewise. * doc/c-bpf.texi (BPF Instructions): Document the signed load instructions.
2023-07-21bpf: opcodes, gas: support for signed register move V4 instructionsJose E. Marchesi2-0/+17
This commit adds the signed register move (movs) instructions introduced in the BPF ISA version 4, including opcodes and assembler tests. Tested in bpf-unknown-none. include/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (BPF_OFFSET16_MOVS8): Define. (BPF_OFFSET16_MOVS16): Likewise. (BPF_OFFSET16_MOVS32): Likewise. (enum bpf_insn_id): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R. opcodes/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R instructions. and MOVS32I instructions. gas/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/bpf/alu.s: Test movs instructions. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu.d: Add expected results. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
2023-07-21bpf: add missing bpf-dis.c to opcodes/Makefile.amJose E. Marchesi3-0/+8
This was breaking --enable-targets=all builds. opcodes/ChangeLog: 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com> * Makefile.am (TARGET64_LIBOPCODES_CFILES): Add missing bpf-dis.c * Makefile.in: Regenerate.
2023-07-21DesCGENization of the BPF binutils portJose E. Marchesi12-6380/+680
CGEN is cool, but the BPF architecture is simply too bizarre for it. The weird way of BPF to handle endianness in instruction encoding, the weird C-like alternative assembly syntax, the weird abuse of multi-byte (or infra-byte) instruction fields as opcodes, the unusual presence of opcodes beyond the first 32-bits of some instructions, are all examples of what makes it a PITA to continue using CGEN for this port. The bpf.cpu file is becoming so complex and so nested with p-macros that it is very difficult to read, and quite challenging to update. Also, every time we are forced to change something in CGEN to accommodate BPF requirements (which is often) we have to do extensive testing to make sure we do not break any other target using CGEN. This is getting un-maintenable. So I have decided to bite the bullet and revamp/rewrite the port so it no longer uses CGEN. Overall, this involved: * To remove the cpu/bpf.{cpu,opc} descriptions. * To remove the CGEN generated files. * To replace the CGEN generated opcodes table with a new hand-written opcodes table for BPF. * To replace the CGEN generated disassembler wih a new disassembler that uses the new opcodes. * To replace the CGEN generated assembler with a new assembler that uses the new opcodes. * To replace the CGEN generated simulator with a new simulator that uses the new opcodes. [This is pushed in GDB in another patch.] * To adapt the build systems to the new situation. Additionally, this patch introduces some extensions and improvements: * A new BPF relocation BPF_RELOC_BPF_DISP16 plus corresponding ELF relocation R_BPF_GNU_64_16 are added to the BPF BFD port. These relocations are used for section-relative 16-bit offsets used in load/store instructions. * The disassembler now has support for the "pseudo-c" assembly syntax of BPF. What dialect to use when disassembling is controlled by a command line option. * The disassembler now has support for dumping instruction immediates in either octal, hexadecimal or decimal. The used output base is controlled by a new command-line option. * The GAS BPF test suite has been re-structured and expanded in order to test the disassembler pseudoc syntax support. Minor bugs have been also fixed there. The assembler generic tests that were disabled for bpf-*-* targets due to the previous implementation of pseudoc syntax are now re-enabled. Additional tests have been added to test the new features of the assembler. .dump files are no longer used. * The linker BPF test suite has been adapted to the command line options used by the new disassembler. The result is very satisfactory. This patchs adds 3448 lines of code and removes 10542 lines of code. Tested in: * Target bpf-unknown-none with 64-bit little-endian host and 32-bit little-endian host. * Target x86-64-linux-gnu with --enable-targets=all Note that I have not tested in a big-endian host yet. I will do so once this lands upstream so I can use the GCC compiler farm. I have not included ChangeLog entries in this patch: these would be massive and not very useful, considering this is pretty much a rewrite of the port. I beg the indulgence of the global maintainers.
2023-07-21x86: adjust disassembly of insns operating on selector valuesJan Beulich1-6/+6
Bring disassembly back in line with what the assembler accepts, thus also making it self-consistent (with, in particular selector load/store insns). While there further add D to all affected insns except ARPL (where S is used, matching LAR/LSL), to also behave correctly in suffix- always mode. While there also hook up the Intel variant of the LKGS test.
2023-07-21x86: simplify disassembly of LAR/LSLJan Beulich1-14/+2
For whatever reason in c9f5b96bdab0 ("x86: correct handling of LAR and LSL") I didn't realize that we can easily use Sv instead of going through mod_table[]. Redo this aspect of that change.
2023-07-19Updated Romainian translation for the opcodes directoryNick Clifton1-374/+344
2023-07-18RISC-V: Supports Zcb extension.Jiawei2-0/+42
This patch support Zcb extension, contains new compressed instructions, some instructions depend on other existed extension, like 'zba', 'zbb' and 'zmmul'. Zcb also imply Zca extension to enable the compressing features. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/zcb.d: New test. * testsuite/gas/riscv/zcb.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_C_LBU): New opcode. (MASK_C_LBU): New mask. (MATCH_C_LHU): New opcode. (MASK_C_LHU): New mask. (MATCH_C_LH): New opcode. (MASK_C_LH): New mask. (MATCH_C_SB): New opcode. (MASK_C_SB): New mask. (MATCH_C_SH): New opcode. (MASK_C_SH): New mask. (MATCH_C_ZEXT_B): New opcode. (MASK_C_ZEXT_B): New mask. (MATCH_C_SEXT_B): New opcode. (MASK_C_SEXT_B): New mask. (MATCH_C_ZEXT_H): New opcode. (MASK_C_ZEXT_H): New mask. (MATCH_C_SEXT_H): New opcode. (MASK_C_SEXT_H): New mask. (MATCH_C_ZEXT_W): New opcode. (MASK_C_ZEXT_W): New mask. (MATCH_C_NOT): New opcode. (MASK_C_NOT): New mask. (MATCH_C_MUL): New opcode. (MASK_C_MUL): New mask. (DECLARE_INSN): New opcode. * opcode/riscv.h (EXTRACT_ZCB_BYTE_UIMM): New inline func. (EXTRACT_ZCB_HALFWORD_UIMM): Ditto. (ENCODE_ZCB_BYTE_UIMM): Ditto. (ENCODE_ZCB_HALFWORD_UIMM): Ditto. (VALID_ZCB_BYTE_UIMM): Ditto. (VALID_ZCB_HALFWORD_UIMM): Ditto. (enum riscv_insn_class): New extension class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): New operators. * riscv-opc.c: New instructions.
2023-07-14Fix loongarch build with gcc-4.5Alan Modra1-1/+1
* loongarch-opc.c (loongarch_alias_opcodes): Don't trigger gcc-4.5 bug in handling of struct initialisation.
2023-07-11x86: simplify table-referencing macrosJan Beulich1-17/+15
First of all it is entirely unclear why THREE_BYTE_TABLE_PREFIX() was introduced by bf890a93a7c4. Nothing uses the .prefix_requirement values from the two relevant entries. And then having VEX_Cn_TABLE() and friends take arguments is misleading. These aren't used (or pointlessly used in the case of VEX_C5_TABLE); the respective table index is decoded from the insn (or implied in the case of VEX_C5_TABLE).
generated by cgit v1.1 at 2025-01-01 10:17:40 +0000