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2018-09-13x86: drop bogus IgnoreSize from GNFI insnsJan Beulich3-12/+17
2018-09-13x86: drop bogus IgnoreSize from PCLMUL/VPCLMUL insnsJan Beulich3-32/+37
2018-09-13x86: drop bogus IgnoreSize from AES/VAES insnsJan Beulich3-44/+49
2018-09-13x86: drop bogus IgnoreSize from SSE4.2 insnsJan Beulich3-20/+26
2018-09-13x86: drop bogus IgnoreSize from SSE4.1 insnsJan Beulich3-126/+132
2018-09-13x86: drop bogus IgnoreSize from SSSE3 insnsJan Beulich3-64/+70
2018-09-13x86: drop bogus IgnoreSize from SSE3 insnsJan Beulich3-36/+41
2018-09-13x86: drop bogus IgnoreSize from SSE2 insnsJan Beulich3-416/+421
2018-09-13x86: drop bogus IgnoreSize from SSE insnsJan Beulich3-118/+123
2018-09-13x86: drop unnecessary {,No}Rex64Jan Beulich3-10/+16
2018-09-13x86: also allow D on 3-operand insnsJan Beulich3-96/+18
2018-09-13x86: use D attribute also for SIMD templatesJan Beulich4-1277/+165
2018-09-13x86-64: bndmk, bndldx, and bndstx don't allow RIP-relative addressingJan Beulich2-3/+21
2018-09-08S12Z: Make disassebler work for --enable-targets=all config.John Darrington2-0/+5
2018-08-31RISC-V: Correct the requirement of compressed floating point instructionsJim Wilson2-16/+21
2018-08-30RISC-V: Allow instruction require more than one extensionJim Wilson3-630/+636
2018-08-29sparc/leon: add support for partial write psr instructionMartin Aberg2-0/+13
2018-08-29[MIPS] Add Loongson 2K1000 proccessor support.Chenghua Xu2-0/+9
2018-08-29[MIPS] Add Loongson 3A2000/3A3000 proccessor support.Chenghua Xu2-0/+9
2018-08-29[MIPS] Add Loongson 3A1000 proccessor support.Chenghua Xu3-2/+14
2018-08-29[MIPS/GAS] Add Loongson EXT2 Instructions support.Chenghua Xu3-0/+26
2018-08-29[MIPS/GAS] Split Loongson EXT Instructions from loongson3a.Chenghua Xu3-65/+88
2018-08-29[MIPS/GAS] Split Loongson CAM Instructions from loongson3aChenghua Xu3-6/+30
2018-08-21Use operand->extract to provide defaults for optional PowerPC operandsAlan Modra3-48/+82
2018-08-21Fix s12z test regexpsAlan Modra1-4/+3
2018-08-20Tidy bit twiddlingAlan Modra2-10/+12
2018-08-18Opcodes: (BRCLR / BRSET) Disassemble reserved codes instead of aborting.John Darrington2-20/+27
2018-08-18S12Z: Move opcode header to public include directory.John Darrington3-72/+5
2018-08-14x86-64: Display eiz for address with the addr32 prefixH.J. Lu2-7/+29
2018-08-11x86: Add CpuCMOV and CpuFXSRH.J. Lu6-7974/+8033
2018-08-06[ARC] Update handling AUX-registers.claziss2-376/+379
2018-08-06x86: fold RegEip/RegRip and RegEiz/RegRizJan Beulich4-18/+27
2018-08-03x86: drop NoRex64 from {,v}pmov{s,z}x*Jan Beulich3-48/+55
2018-08-03x86: drop "mem" operand type attributeJan Beulich5-17991/+17995
2018-08-01csky regenAlan Modra2-0/+5
2018-07-31Correct previous update - new translation for the opcodes subdirectory.Nick Clifton2-393/+1909
2018-07-31x86: also optimize KXOR{D,Q} and KANDN{D,Q}Jan Beulich3-8/+13
2018-07-31x86: fold various AVX512 templates with so far differing Masking attributesJan Beulich4-1443/+330
2018-07-31x86/Intel: correct permitted operand sizes for AVX512 scatter/gatherJan Beulich3-126/+132
2018-07-31x86: drop CpuVREXJan Beulich5-4351/+4355
2018-07-30RISC-V: Set insn info fields correctly when disassembling.Jim Wilson3-178/+210
2018-07-30Add support for the C_SKY series of processors.Andrew Jenner9-0/+9228
2018-07-27Re: PowerPC Improve support for Gekko & BroadwayAlan Modra2-6/+12
2018-07-26PowerPC Improve support for Gekko & BroadwayAlex Chadwick3-5/+89
2018-07-25x86: Expand Broadcast to 3 bitsH.J. Lu4-398/+479
2018-07-24PR23430, Indices misspelledAlan Modra2-1/+6
2018-07-24x86-64: correct AVX512F vcvtsi2s{d,s} handlingJan Beulich4-40/+48
2018-07-23[ARC] Fix decoding of w6 signed short immediate.Claudiu Zissulescu2-1/+9
2018-07-23[ARC] Allow vewt instruction for ARC EM family.Claudiu Zissulescu2-2/+9
2018-07-23power9 mfupmc/mtupmcAlan Modra2-0/+24
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