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AgeCommit message (Expand)AuthorFilesLines
2022-01-14x86: reduce AVX512 FP set of insns decoded through vex_w_table[]Jan Beulich5-268/+42
2022-01-14x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[]Jan Beulich4-137/+77
2022-01-06aarch64: Add support for new SME instructionsRichard Sandiford2-302/+338
2022-01-06x86: drop NoAVX insn attributeJan Beulich4-4520/+4516
2022-01-06x86: drop NoAVX from POPCNTJan Beulich2-2/+2
2022-01-06x86: drop some "comm" template parametersJan Beulich2-90/+90
2022-01-06x86: templatize FMA insn templatesJan Beulich2-1016/+830
2022-01-05opcodes: Make i386-dis.c thread-safeVladimir Mezentsev1-1738/+1774
2022-01-02Update year range in copyright notice of binutils filesAlan Modra282-286/+301
2022-01-01unify 64-bit bfd checksMike Frysinger5-4/+265
2021-12-24RISC-V: Hypervisor ext: support Privileged Spec 1.12Vineet Gupta1-0/+21
2021-12-17x86: Terminate mnemonicendp in swap_operand()Vladimir Mezentsev1-0/+1
2021-12-16RISC-V: Support svinval extension with frozen version 1.0.Nelson Chu1-0/+7
2021-12-03aarch64: Fix uninitialised memoryRichard Sandiford2-1/+3
2021-12-03Revert "Re: Don't compile some opcodes files when bfd is 32-bit only"Alan Modra2-10/+10
2021-12-02aarch64: Add BC instructionRichard Sandiford2-47/+65
2021-12-02aarch64: Enforce P/M/E order for MOPS instructionsRichard Sandiford3-15/+127
2021-12-02aarch64: Add support for +mopsRichard Sandiford9-32/+1535
2021-12-02aarch64: Add Armv8.8-A system registersRichard Sandiford1-0/+5
2021-12-02aarch64: Add id_aa64isar2_el1Richard Sandiford1-0/+1
2021-12-02aarch64: Tweak insn sequence codeRichard Sandiford1-26/+22
2021-12-02aarch64: Add maximum immediate value to aarch64_sys_regRichard Sandiford2-35/+26
2021-12-02Allow the --visualize-jumps feature to work with the AVR disassembler.Marcus Nilsson2-5/+37
2021-11-30aarch64: Add missing system registers [PR27145]Richard Sandiford1-1/+166
2021-11-30aarch64: Make LOR registers conditional on +lorRichard Sandiford1-4/+6
2021-11-30aarch64: Remove ZIDR_EL1Richard Sandiford1-1/+0
2021-11-30aarch64: Allow writes to MFAR_EL3Richard Sandiford1-1/+1
2021-11-30aarch64: Mark PMSIDR_EL1 as read-onlyRichard Sandiford1-1/+1
2021-11-30aarch64: Remove duplicate system register entriesRichard Sandiford1-7/+1
2021-11-30RISC-V: The vtype immediate with more than the defined 8 bits are preserved.Nelson Chu1-1/+1
2021-11-30RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved.Nelson Chu2-3/+5
2021-11-29opcodes: enable silent build rulesMike Frysinger4-54/+94
2021-11-26opcodes/riscv: add disassembler options support to libopcodesAndrew Burgess2-9/+147
2021-11-25Fix building the AArch64 assembler and disassembler when assertions are disab...Nick Clifton4-32/+45
2021-11-25Updated French translation for the opcodes directory.Nick Clifton2-236/+264
2021-11-23Update bug reporting addressAlan Modra1-1/+1
2021-11-18Re: Don't compile some opcodes files when bfd is 32-bit onlyAlan Modra2-10/+10
2021-11-18RISC-V: Add instructions and operand set for z[fdq]inxjiawei2-148/+152
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus10-191/+387
2021-11-17aarch64: [SME] Add new SME system registersPrzemyslaw Wirkus1-1/+11
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus10-1514/+1641
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus9-236/+605
2021-11-17aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus6-140/+204
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus10-175/+363
2021-11-17aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus6-133/+547
2021-11-17aarch64: [SME] Add +sme option to -marchPrzemyslaw Wirkus1-0/+11
2021-11-17RISC-V: Support rvv extension with released version 1.0.Nelson Chu2-0/+893
2021-11-16RISC-V: Scalar crypto instructions and operand set.jiawei2-20/+80
2021-11-12Don't compile some opcodes files when bfd is 32-bit onlyAlan Modra5-56/+74
2021-11-11RISC-V: Dump objects according to the elf architecture attribute.Nelson Chu1-6/+26
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