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2010-11-25Update translationsAlan Modra5-531/+532
2010-11-11 bfd/Nick Clifton3-59/+71
* archures.c (bfd_mach_mips_loongson_3a): Defined. * bfd-in2.h (bfd_mach_mips_loongson_3a): Defined. * cpu-mips.c (I_loongson_3a): New add. (arch_info_struct): Add loongson_3a. * elfxx-mips.c (_bfd_elf_mips_mach): Add loongson_3a. (mips_set_isa_flags): Add loongson_3a. (mips_mach_extensions): Add loongson_3a in MIPS64 extensions. binutils/ * readelf.c (get_machine_flags): Add loongson-3a. gas/ * config/tc-mips.c (mips_cpu_info_table): Add loongson3a in MIPS 64. * doc/c-mips.texi (MIPS cpu): Add loongson3a. include/ * elf/mips.h (E_MIPS_MACH_LS3A): Defined. * opcode/mips.h (INSN_LOONGSON_3A): Defined. (CPU_LOONGSON_3A): Defined. (OPCODE_IS_MEMBER): Add LOONGSON_3A. opcodes/ * mips-dis.c (mips_arch_choices): Add loongson3a. * mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A. (mips_builtin_opcodes): Modify some instructions' membership from IL2F to IL2F|IL3A, since these instructions are supported by Loongson_3A.
2010-11-10Updated translations.Nick Clifton2-220/+225
2010-11-05bfd/Tristan Gingold2-170/+166
2010-11-05 Tristan Gingold <gingold@adacore.com> * po/bfd.pot: Regenerate binutils/ 2010-11-05 Tristan Gingold <gingold@adacore.com> * po/binutils.pot: Regenerate gas/ 2010-11-05 Tristan Gingold <gingold@adacore.com> * po/gas.pot: Regenerate * po/POTFILES.in: Regenerate gprof/ 2010-11-05 Tristan Gingold <gingold@adacore.com> * po/gprof.pot: Regenerate ld/ 2010-11-05 Tristan Gingold <gingold@adacore.com> * po/ld.pot: Regenerate * po/POTFILES.in: Regenerate opcodes/ 2010-11-05 Tristan Gingold <gingold@adacore.com> * po/opcodes.pot: Regenerate
2010-10-28 * mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld".Maciej W. Rozycki2-1/+5
2010-10-282010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel2-3/+7
* config/tc-s390.c (md_begin): Only add to hash table if cpu and mode mask fit. 2010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-opc.txt: cfxr, cfdr and cfer z900 -> g5.
2010-10-252010-10-25 Chao-ying Fu <fu@mips.com>Chao-ying Fu2-6/+10
* mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.
2010-10-25 bfd/Nathan Sidwell2-0/+6
* elf32-tic6x.c: Add attribution. gas/ * config/tc-tic6x.c: Add attribution. opcodes/ * tic6x-dis.c: Add attribution.
2010-10-21 * Makefile.am (CLEANFILES): Add stamp-lm32. Sort.Alan Modra3-6/+13
* Makefile.in: Regenerate.
2010-10-18 opcodes/Maciej W. Rozycki2-2/+9
* mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB macros before their corresponding MIPS III hardware instructions. gas/ * config/tc-mips.c (macro)[M_LD_OB, M_SD_OB]: Handle 64-bit ABIs. gas/testsuite/ * gas/mips/lineno.s: Convert to o32. * gas/mips/lineno.d: Adjust patterns accordingly. Force the o32 ABI.
2010-10-16Add CpuNop to CPU_GENERIC64_FLAGS.H.J. Lu3-2/+8
gas/testsuite/ 2010-10-16 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run x86-64-nops-1-g64. * gas/i386/x86-64-nops-1.d: Remove -mtune=generic64. * gas/i386/x86-64-nops-1-g64.d: New. opcodes/ 2010-10-16 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS. * i386-init.h: Regenerated.
2010-10-15gas: blackfin: fix encoding of BYTEOP2M insnMike Frysinger2-8/+12
The BYTEOP2M parser incorrectly calls BYTEOP2P to generate the opcode. Once we've fixed that, it's easy to see that the disassembler also likes to decode this insn incorrectly. So fix that and then add some tests. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-10-14Remove CheckRegSize from movq.H.J. Lu3-4/+9
2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Remove CheckRegSize from movq. * i386-tbl.h: Regenerated.
2010-10-14Remove CheckRegSize from instructions with 0, 1 or fixed operands.H.J. Lu3-68/+74
2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Remove CheckRegSize from instructions with 0, 1 or fixed operands. * i386-tbl.h: Regenerated.
2010-10-14Add CheckRegSize to instructions which require register size check.H.J. Lu5-7601/+7616
gas/ 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (match_template): Check checkregsize instead of w for register size check. gas/testsuite/ 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run inval-reg. * gas/i386/inval-reg.l: New. * gas/i386/inval-reg.s: Likewise. opcodes/ 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Add CheckRegSize. * i386-opc.h (CheckRegSize): New. (i386_opcode_modifier): Add checkregsize. * i386-opc.tbl: Add CheckRegSize to instructions which require register size check. * i386-tbl.h: Regenerated.
2010-10-11binutils/:Andreas Schwab2-3/+8
* binutils-all/m68k/objdump.exp: Add fnop test. * binutils-all/m68k/fnop.s: New file. opcodes/: * m68k-opc.c (m68k_opcodes): Move fnop before fbf.
2010-10-112010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel3-5/+11
* s390-opc.c: Make the instruction masks for the load/store on condition instructions to cover the condition code mask as well. * s390-opc.txt: lgoc -> locg and stgoc -> stocg. 2010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/zarch-z196.d: Adjust the load/store on condition instructions. * gas/s390/zarch-z196.s: Likewise.
2010-10-11opcodes/Jan Kratochvil3-4/+11
* Makefile.am (libopcodes_a_SOURCES): New as empty. * Makefile.in: Regenerate.
2010-10-09cgen/Alan Modra14-407/+423
* utils-cgen.scm (gen-attr-accessors): Rename bool attribute to bool_. * cpu/mep.opc (mep_cgen_insn_supported): Ditto. include/opcode/ * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_. (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise. opcodes/ * fr30-desc.h: Regenerate. * frv-desc.h: Regenerate. * ip2k-desc.h: Regenerate. * iq2000-desc.h: Regenerate. * lm32-desc.h: Regenerate. * m32c-desc.h: Regenerate. * m32r-desc.h: Regenerate. * mep-desc.h: Regenerate. * mep-opc.c: Regenerate. * mt-desc.h: Regenerate. * openrisc-desc.h: Regenerate. * xc16x-desc.h: Regenerate. * xstormy16-desc.h: Regenerate.
2010-10-08Fix build with -DDEBUG=7Alan Modra4-12/+26
2010-10-07gas/Bernd Schmidt2-2/+9
* config/tc-tic6x.c (tic6x_try_encode): Correct encoding of fstg field in SPKERNEL instructions. opcodes/ * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field in SPKERNEL instructions. gas/testsuite/ * gas/tic6x/insns-c674x-sploop.d: Add two more sploop/spkernel tests. * gas/tic6x/insns-c674x-sploop.s: Likewise.
2010-10-02Remove duplicated RMAL.H.J. Lu2-1/+5
2010-10-02 H.J. Lu <hongjiu.lu@intel.com> PR binutils/12076 * i386-dis.c (RMAL): Remove duplicate.
2010-09-30 * s390-mkopc.c (main): Exit with error 1 if sscanf failsPierre Muller2-1/+9
to parse all 6 parameters.
2010-09-30 * s390-mkopc.c (main): Change description array size to 80.Pierre Muller2-2/+7
Add maximum length of 79 to description parsing.
2010-09-27Fix unportable shell quoting.Ralf Wildenhues2-1/+5
/: Sync from GCC: PR bootstrap/44621 * configure.ac: Fix unportable shell quoting. * configure: Regenerate. config/: * po.m4 (AM_PO_SUBDIRS): Fix unportable shell quoting. bfd/: * configure: Regenerate. gas/: * configure: Regenerate. gold/: * configure: Regenerate. intl/: * configure: Regenerate. ld/: * configure: Regenerate. opcodes/: * configure: Regenerate. binutils/: * configure: Regenerate. gprof/: * configure: Regenerate.
2010-09-272010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel4-4/+165
* s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196. (main): Recognize the new CPU string. * s390-opc.c: Add new instruction formats and masks. * s390-opc.txt: Add new z196 instructions. 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * opcode/s390.h: Add S390_OPCODE_Z196 to enum s390_opcode_cpu_val. 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * config/tc-s390.c: (md_parse_option): New option -march=z196. * doc/c-s390.texi: Document new option. 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/s390.exp: Run the zarch-z196 test. * gas/s390/zarch-z196.d: Add new instructions. * gas/s390/zarch-z196.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise.
2010-09-272010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel4-14/+47
* s390-dis.c (print_insn_s390): Pick instruction with most specific mask. * s390-opc.c: Add unused bits to the insn mask. * s390-opc.txt: Reorder some instructions to prefer more recent versions. 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/esa-g5.d: Adjust serveral instructions. * gas/s390/esa-reloc.d: Likewise. * gas/s390/esa-z990.d: Likewise. * gas/s390/zarch-reloc.d: Likewise. * gas/s390/zarch-z10.d: Likewise. * gas/s390/zarch-z9-ec.d: Likewise. * gas/s390/zarch-z900.d: Likewise. 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * ld-s390/tlsbin.dd: bcr 0,%r7 -> nopr %r7. * ld-s390/tlsbin_64.dd: Likewise. * ld-s390/tlspic.dd: Likewise. * ld-s390/tlspic_64.dd: Likewise.
2010-09-272010-09-27 Tejas Belagod <tejas.belagod@arm.com>Matthew Gretton-Dann2-2/+11
* gas/config/tc-arm.c (do_neon_ldr_str): Deprecate ARM-mode PC-relative VSTR, issue an error in THUMB mode. * opcodes/arm_dis.c (print_insn_coprocessor): Apply off-by-alignment correction to unaligned PCs while printing comment. * gas/testsuite/gas/arm/vldr.s: New test for pc-relative VLDR disassembly comment. * gas/testsuite/gas/arm/vldr.d: Likewise. * gas/testsuite/gas/arm/vstr-bad.s: New test for PC-relative VSTR. * gas/testsuite/gas/arm/vstr-thumb-bad.l: Likewise. * gas/testsuite/gas/arm/vstr-thumb-bad.d: Likewise. * gas/testsuite/gas/arm/vstr-arm-bad.l: Likewise. * gas/testsuite/gas/arm/vstr-arm-bad.d: Likewise.
2010-09-23 * bfd/bfd-in2.h (BFD_RELOC_ARM_HVC): New enum value.Matthew Gretton-Dann2-16/+151
* gas/config/tc-arm.c (arm_ext_virt): New variable. (arm_reg_type): Add REG_TYPE_RNB for banked registers. (reg_entry): Allow registers to be larger than a byte. (reg_alias): Fix type warning. (parse_operands): Parse banked registers when appropriate. (do_mrs): Add support for Virtualization Extensions. (do_hvc): New function. (do_t_mrs): Add support for Virtualization Extensions. (do_t_msr): Likewise. (do_t_hvc): New function. (SPLRBANK): New define. (reg_names): Add banked registers. (insns): Add support for Virtualization Extensions. (md_apply_fixup): Likewise. (arm_cpus): -mcpu=cortex-a15 implies the Virtualization Extensions. (arm_extensions): Add 'virt' extension. (aeabi_set_public_attributes): Add support for Virtualization Extensions. * gas/doc/c-arm.texi: Document 'virt' extension. * gas/testsuite/gas/arm/armv7-a+virt.d: New test. * gas/testsuite/gas/arm/armv7-a+virt.s: Likewise. * gas/testsuite/gas/arm/attr-march-all.d: Update for Virtualization Extensions. * gas/testsuite/gas/arm/attr-march-armv7-a+sec+virt.d: New test. * gas/testsuite/gas/arm/attr-march-armv7-a+virt.d: Likewise. * include/opcode/arm.h (ARM_EXT_VIRT): New define. (ARM_ARCH_V7A_IDIV_MP_SEC): Rename... (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization Extensions. * opcodes/arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support. (thumb32_opcodes): Likewise. (banked_regname): New function. (print_insn_arm): Add Virtualization Extensions support. (print_insn_thumb32): Likewise.
2010-09-23 * gas/config/tc-arm.c (arm_ext_adiv): New variable.Matthew Gretton-Dann2-0/+9
(do_div): New function. (insns): Accept UDIV and SDIV in ARM state. (arm_cpus): The cortex-a15 option has all current v7-A extensions. (arm_extensions): Add 'idiv' extension. (aeabi_set_public_attributes): Update Tag_DIV_use values for the Integer Divide extension. * gas/doc/c-arm.texi: Document the idiv extension. * gas/testsuite/gas/arm/armv7-a+idiv.d: New test. * gas/testsuite/gas/arm/armv7-a+idiv.s: Likewise. * gas/testsuite/gas/arm/attr-march-all.d: Update for Integer divide extension. * gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d: New test. * include/opcode/arm.h (ARM_AEXT_ADIV): New define. (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise. * opcodes/arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in ARM state.
2010-09-23 * gas/config/tc-arm.c (arm_ext_v6z): Remove.Matthew Gretton-Dann2-3/+10
(arm_ext_sec): New variable. (do_t_smc): In Thumb state SMC requires v7-A. (insns): Make SMC depend on Security Extensions. (arm_cpus): All -mcpu=cortex-a* options have the Security Extensions. (arm_extensions): Add 'sec' extension. (cpu_arch_ver): Reorder. (aeabi_set_public_attributes): Emit Tag_Virtualization_use as appropriate. * gas/doc/c-arm.texi: Document Security Extensions. * gas/testsuite/gas/arm/attr-march-all.d: Update for Security Extensions.. * gas/testsuite/gas/arm/attr-march-armv6k+sec.d: New test. * gas/testsuite/gas/arm/attr-march-armv6z.d: Update for Security Extensions. * gas/testsuite/gas/arm/attr-march-armv6zk.d: Likewise. * gas/testsuite/gas/arm/attr-march-armv6zkt2.d: Likewise. * gas/testsuite/gas/arm/attr-march-armv6zt2.d: Likewise. * gas/testsuite/gas/arm/attr-march-armv7-a+sec.d: New test. * gas/testsuite/gas/arm/attr-mcpu.d: Update for Security Extensions. * gas/testsuite/gas/arm/thumb32.d: Likewise. * gas/testsuite/gas/arm/thumb32.s: Likewise. * include/opcode/arm.h (ARM_EXT_V6Z): Remove. (ARM_EXT_SEC): New define. (ARM_AEXT_V6Z): Use Security Extensions. (ARM_AEXT_V6ZK): Likeiwse. (ARM_AEXT_V6ZT2): Likewise. (ARM_AEXT_V6ZKT2): Likewise. (ARM_AEXT_V7_ARM): Base v7 does not have Security Extensions. (ARM_ARCH_V7A_SEC): New define. (ARM_ARCH_V7A_MP): Rename... (ARM_ARCH_V7A_MP_SEC): ...to this and add Security Extensions. * ld/testsuite/ld-arm/attr-merge-6.attr: Update for Security Extensions. * ld/testsuite/ld-arm/attr-merge-7.attr: Likewise. * opcodes/arm-dis.c (arm_opcodes): SMC implies Security Extensions. (thumb32_opcodes): Likewise.
2010-09-23 * gas/config/tc-arm.c (arm_ext_mp): Add.Matthew Gretton-Dann2-0/+11
(do_pld): Update comment. (insns): Add support for pldw. (arm_cpus): Update cortex-a5, cortex-a9, and cortex-a15 to support MP extension. (arm_extensions): Add 'mp' extension. (aeabi_set_public_attributes): Emit correct build attribute when MP extension is enabled. * gas/doc/c-arm.texi: Update for MP extensions. * gas/testsuite/gas/arm/arch7a-mp.d: Add. * gas/testsuite/gas/arm/arch7ar-mp.s: Likewise. * gas/testsuite/gas/arm/arch7r-mp.d: Likewise. * gas/testsuite/gas/arm/armv2-mp-bad.d: Likewise. * gas/testsuite/gas/arm/armv2-mp-bad.l: Likewise. * gas/testsuite/gas/arm/attr-march-all.d: Update for MP extension. * gas/testsuite/gas/arm/attr-march-armv7-a+mp.d: Add. * gas/testsuite/gas/arm/attr-march-armv7-r+mp.d: Likewise. * include/opcode/arm.h (ARM_EXT_MP): Add. (ARM_ARCH_V7A_MP): Likewise. * opcodes/arm-dis.c (arm_opcodes): Add support for pldw. (thumb32_opcodes): Likewise.
2010-09-22opcodes: blackfin: fix decoding of 32bit addresses on 64bit systemsMike Frysinger2-0/+7
The Blackfin ISA is very exact with regards to address truncation when under/over flowing its 32bit range. On a 32bit system, things work the same and so addresses are decoded properly. On a 64bit system though, the decoded addresses may include the bits that are supposed to have been truncated. So force a 32bit truncation after the address has been calculated. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22opcodes: blackfin: fix decoding of all register move insnsMike Frysinger2-12/+34
Many register move insns were not being decoded properly, so rewrite the whole function to be a bit more manageable in terms of valid combinations. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22opcodes: blackfin: fix decoding of many invalid insnsMike Frysinger2-21/+127
The Blackfin disassembler was originally based on the premise of parsing valid opcodes all the time, so some of the opcode checking can be a bit fuzzy. This is exemplified in decoding of parallel insns where many times things are decoded as invalid when in reality, they may not be used in parallel combinations. So add parallel checking to most insn decoding routines so we see ILLEGAL and not just whatever insn happens to be close to a valid mnemonic, as well as some additional sub-opcode checks. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22opcodes: blackfin: mark push/pop insns with a P6/P7 range as illegalMike Frysinger2-0/+7
The push/pop multiple insn has a 3 bit field for the P register range, but only values of 0...5 are valid (P0 - P5). There is no such P6 or P7 register, so mark these insns as illegal. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22opcodes: blackfin: fix decoding of vector shift insn w/saturationMike Frysinger2-1/+5
The saturation bit was missed when decoding a vector shift insn leading to the output looking the same as the non-saturating insn. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22opcodes: blackfin: decode all ASTAT bitsMike Frysinger2-8/+25
All ASTAT bits work in the hardware even though they aren't part of the official Blackfin ISA. So decode every ASTAT field to make the output a bit nicer when working with hand generated opcodes. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22opcodes: blackfin: decode insns with invalid register as illegalMike Frysinger2-14/+28
Sometimes the encoding in the opcode is a 4 bit field which defines a register number. However, register numbers are only 0-7, so make sure we call illegal for when the opcode register number is greater than 8. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22gas: blackfin: fix DBG/DBGCMPLX insn encodingMike Frysinger2-1/+5
Some extended registers when given to the DBG/DBGCMPLX pseudo insns are not encoded properly. So fix them, fix the display of them when being disassembled, and add testcases. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22opcodes/gas: blackfin: handle more ASTAT flagsMike Frysinger2-4/+16
Support a few more ASTAT bits with the standard insns that operate on ASTAT bits directly. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22opcodes/gas: blackfin: support OUTC debug insnMike Frysinger2-4/+23
The disassembler has partial (but incomplete/broken) support already for the pseudo debug insn OUTC, so let's fix it up and finish it. And now that the disassembler can handle it, make sure our assembler can output it too. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22opcodes: blackfin: fix decoding of LSHIFT insnsMike Frysinger2-2/+7
The Blackfin ISA does not have a "SHIFT" insn, it has either LSHIFT, ASHIFT, or BXORSHIFT. So be specific when disassembling. As fall out of this change, we need to update some assembler tests. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-22opcodes: blackfin: constify formatting related structuresMike Frysinger2-22/+30
No need for these local structures related to formatting of output to be writable, so constify the whole shebang. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2010-09-172010-09-17 Tejas Belagod <tejas.belagod@arm.com>Matthew Gretton-Dann2-0/+5
* config/tc-arm.c (insns): Change MRC entry to accept APSR_RR instead of just RR. 2010-09-17 Tejas Belagod <tejas.belagod@arm.com> * gas/arm/copro.s: Add test for APSR_nzcv as a MRC operand. * gas/arm/copro.d: Change pc in MRC to disassemble as APSR_nzcv. Also add disassembly for test added in copro.s 2010-09-17 Tejas Belagod <tejas.belagod@arm.com> * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
2010-09-14 opcodes/Maciej W. Rozycki2-0/+10
* mips-opc.c (mips_builtin_opcodes): Add "sync_acquire", "sync_mb", "sync_release", "sync_rmb" and "sync_wmb". gas/testsuite/ * gas/mips/mips32r2-sync.d: New test for MIPS32r2 "sync" instruction variants. * gas/mips/octeon@mips32r2-sync.d: Likewise, Octeon version. * gas/mips/mips32r2-sync.s: Source for the new test. * gas/mips/mips.exp: Run the new test.
2010-09-10 * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type forPierre Muller2-11/+16
dlx_insn_type array.
2010-08-31Fix "pushw imm16" for x86-64 disassembler.H.J. Lu2-38/+40
gas/testsuite/ 2010-08-31 H.J. Lu <hongjiu.lu@intel.com> PR binutils/11960 * gas/i386/opcode-intel.d: Updated. * gas/i386/x86-64-opcode.d: Likewise. * gas/i386/x86-64-opcode.s: Add a "pushw imm16" test. opcodes/ 2010-08-31 H.J. Lu <hongjiu.lu@intel.com> PR binutils/11960 * i386-dis.c (sIv): New. (dis386): Replace Iq with sIv on "pushT". (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT. (x86_64_table): Replace {T|}/{P|} with P. (putop): Add 'w' to 'T'/'P' if needed for Intel syntax. (OP_sI): Update v_mode. Remove w_mode.
2010-08-27opcodes/Nathan Froyd2-4/+9
* ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate on E500 and E500MC.
2010-08-17Replace Eb with Mb on prefetch and prefetchw.H.J. Lu2-2/+7
2010-08-17 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and prefetchw.
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