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According to the picture 28.1 in the current ISA spec, h is no larger the
multi-letter extension, it is a single extension after v. Therefore, this
patch fix the implementation, and use the single h to control hypervisor
CSRs and instructions, which we promised to do before.
bfd/
* elfxx-riscv.c (riscv_supported_std_ext): Added h with version 1.0 after v.
(riscv_supported_std_h_ext): Removed.
(riscv_all_supported_ext): Updated since riscv_supported_std_h_ext is removed.
(riscv_prefix_ext_class): Removed RV_ISA_CLASS_H.
(parse_config): Updated since riscv_prefix_ext_class is removed.
(riscv_recognized_prefixed_ext): Likewise.
(riscv_get_default_ext_version): Likewise.
(riscv_multi_subset_supports): Handle INSN_CLASS_H for hypervisor instructions.
(riscv_multi_subset_supports_ext): Likewise.
gas/
* config/tc-riscv.c (riscv_csr_class): Added CSR_CLASS_H and CSR_CLASS_H_32 for
hypervisor CSRs.
(riscv_csr_address): Likewise.
* testsuite/gas/riscv/csr-version-1p10.d: Updated since hypervisor CSRs are
controlled by single h extension for now.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
* testsuite/gas/riscv/h-ext-32.d: Added h to architecture string.
* testsuite/gas/riscv/h-ext-64.d: Likewise.
* testsuite/gas/riscv/march-fail-single-prefix-h: Removed since h is no
longer multi-letter extension.
* testsuite/gas/riscv/march-fail-unknown-h.d: Likewise.
include/
* opcode/riscv-opc.h: Control hypervisor CSRs by h extension, rather than
the privileged spec verisons.
* opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_H.
opcodes/
* riscv-opc.c (riscv_opcodes): Control hypervisor instructions by h extension.
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For quite some time all callers have been passing 1 / true. While there
fold the final oappend_with_style() calls.
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Commit 384e201e5aec ("x86: properly initialize struct instr_info
instance(s)") was based on an improperly refreshed patch. Correct the
oversight.
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With its movement to the stack, and with the subsequent desire to
initialize the entire instr_info instances, this has become doubly
inefficient. Individual users have better knowledge of how big a buffer
they need, and in a number of cases going through an intermediate buffer
can be avoided altogether.
Having got confirmation that it wasn't intentional to print memory
operand displacements with inconsistent style, print_displacement() is
now using dis_style_address_offset consistently (eliminating the need
for callers to pass in a style).
While touching print_operand_value() also convert its "hex" parameter to
bool. And while altering (and moving) oappend_immediate(), fold
oappend_maybe_intel_with_style() into its only remaining caller. Finally
where doing adjustments, use snprintf() in favor of sprintf().
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Now that op_out[] is an array of pointers, there's no need anymore to
copy strings. Simply swap the pointers.
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By changing the values used for "artificial" prefix values,
all_prefixes[] can be shrunk to array of unsigned char. All that
additionally needs adjusting is the printing of possible apparently
standalone prefixes when recovering from longjmp(): Simply check
whether any prefixes were successfully decoded, to avoid converting
opcode bytes matching the "artificial" values to prefix mnemonics.
Similarly by re-arranging the bits assigned to PREFIX_* mask values
we can fit all segment register masks in a byte and hence shrink
active_seg_prefix to unsigned char.
Somewhat similarly with last_*_prefix representing offsets into the
opcode being disassembled, signed char is sufficient to hold all possible
values.
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Commit 39fb369834a3 ("opcodes: Make i386-dis.c thread-safe") introduced
a lot of uninitialized data. Alan has in particular observed ubsan
taking issue with the loop inverting the order of operands, where
op_riprel[] - an array of bool - can hold values other than 0 or 1.
Move instantiation of struct instr_info into print_insn() (thus having
just a single central point), and make use of C99 dedicated initializers
to fill fields right in the initializer where possible. This way all
fields not explicitly initialized will be zero-filled, which in turn
allows dropping of some other explicit initialization later in the
function or in ckprefix(). Additionally this removes a lot of
indirection, as all "ins->info" uses can simply become "info".
Make one further arrangement though, to limit the amount of data needing
(zero)initializing on every invocation: Convert the op_out structure
member to just an array of pointers, with the actual arrays living
inside print_insn() (and, as befoe, having just their 1st char filled
with nul).
While there, instead of adjusting print_insn()'s forward declaration,
arrange for no such declaration to be needed in the first place.
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The i386 disassembler is pretty complex. Most disassembly is done
indirectly; operands are built into buffers within a struct instr_info
instance, before finally being printed later in the disassembly
process.
Sometimes the operand buffers are built in a different order to the
order in which they will eventually be printed.
Each operand can contain multiple components, e.g. multiple registers,
immediates, other textual elements (commas, brackets, etc).
When looking for how to apply styling I guess the ideal solution would
be to move away from the operands being a single string that is built
up, and instead have each operand be a list of "parts", where each
part is some text and a style. Then, when we eventually print the
operand we would loop over the parts and print each part with the
correct style.
But it feels like a huge amount of work to move from where we are
now to that potentially ideal solution. Plus, the above solution
would be pretty complex.
So, instead I propose a .... different solution here, one that works
with the existing infrastructure.
As each operand is built up, piece be piece, we pass through style
information. This style information is then encoded into the operand
buffer (see below for details). After this the code can continue to
operate as it does right now in order to manage the set of operand
buffers.
Then, as each operand is printed we can split the operand buffer into
chunks at the style marker boundaries, with each chunk being printed
with the correct style.
For encoding the style information I use a single character, currently
\002, followed by the style encoded as a single hex digit, followed
again by the \002 character.
This of course relies on there not being more than 16 styles, but that
is currently true, and hopefully will remain true for the foreseeable
future.
The other major concern that has arisen around this work is whether
the escape character could ever be encountered in output naturally
generated by the disassembler. If this did happen then the escape
characters would be stripped from the output, and the wrong styling
would be applied.
However, I don't believe that this is currently a problem.
Disassembler content comes from a number of sources. First there's
content that copied directly from the i386-dis.c file, this is things
like register names, and other syntax elements (brackets, commas,
etc). We can easily check that the i386-dis.c file doesn't contain
our special character.
The next source of content are immediate operands. The text for these
operands is generated by calls into libc. By selecting a
non-printable character we can be confident that this is not something
that libc will generate as part of an immediate representation.
The other output that appears to be from the disassembler is operands
that contain addresses and (possibly) symbol names. It is quite
possible that a symbol name might contain any special character we
could imagine, so is this a problem?
I don't think it is, we don't actually print address and symbol
operands through the disassembler, instead, the disassembler calls
back to the user (objdump, gdb, etc) to print the address and symbol
on its behalf. This content is printed directly to the output stream,
it does not pass through the i386 disassembler output buffers. As a
result, we never check this particular output for styling escape
characters.
In some (not very scientific) benchmarking on my machine,
disassembling a reasonably large (142M) shared library, I'm not seeing
any significant slow down in disassembler speed with this change.
Most instructions are now being fully syntax highlighted when I
disassemble using the --disassembler-color=extended-color option. I'm
sure that there are probably still a few corner cases that need fixing
up, but we can come back to them later I think.
When disassembler syntax highlighting is not being used, then there
should be no user visible changes after this commit.
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The zhinx extension is a sub-extension in zfinx, corresponding to
zfh extension but use GPRs instead of FPRs.
This patch expanded the zfh insn class define, since zfh and zhinx
use the same opcodes, thanks for Nelson's works.
changelog in V2: Add missing classes of 'zfh' and 'zhinx' in
"riscv_multi_subset_supports_ext".
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New extensions.
(riscv_multi_subset_supports_ext): New extensions.
gas/ChangeLog:
* testsuite/gas/riscv/fp-zhinx-insns.d: New test.
* testsuite/gas/riscv/fp-zhinx-insns.s: New test.
include/ChangeLog:
* opcode/riscv.h (enum riscv_insn_class): New INSN classes.
opcodes/ChangeLog:
* riscv-opc.c: Modify INSN_CLASS.
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While working on another patch[1] I had need to touch this code in
i386-dis.c:
ins->obufp = ins->mnemonicendp;
for (i = strlen (ins->obuf) + prefix_length; i < 6; i++)
oappend (ins, " ");
oappend (ins, " ");
(*ins->info->fprintf_styled_func)
(ins->info->stream, dis_style_mnemonic, "%s", ins->obuf);
What this code does is add whitespace after the instruction mnemonic
and before the instruction operands.
The problem I ran into when working on this code can be seen by
assembling this input file:
.text
nop
retq
Now, when I disassemble, here's the output. I've replaced trailing
whitespace with '_' so that the issue is clearer:
Disassembly of section .text:
0000000000000000 <.text>:
0: 90 nop
1: c3 retq___
Notice that there's no trailing whitespace after 'nop', but there are
three spaces after 'retq'!
What happens is that instruction mnemonics are emitted into a buffer
instr_info::obuf, then instr_info::mnemonicendp is setup to point to
the '\0' character at the end of the mnemonic.
When we emit the whitespace, this is then added starting at the
mnemonicendp position. Lets consider 'retq', first the buffer is
setup like this:
'r' 'e' 't' 'q' '\0'
Then we add whitespace characters at the '\0', converting the buffer
to this:
'r' 'e' 't' 'q' ' ' ' ' ' ' '\0'
However, 'nop' is actually an alias for 'xchg %rax,%rax', so,
initially, the buffer is setup like this:
'x' 'c' 'h' 'g' '\0'
Then in NOP_Fixup we spot that we have an instruction that is an alias
for 'nop', and adjust the buffer to this:
'n' 'o' 'p' '\0' '\0'
The second '\0' is left over from the original buffer contents.
However, when we rewrite the buffer, we don't afjust mnemonicendp,
which still points at the second '\0' character.
Now, when we insert whitespace we get:
'n' 'o' 'p' '\0' ' ' ' ' ' ' ' ' '\0'
Notice the whitespace is inserted after the first '\0', so, when we
print the buffer, the whitespace is not printed.
The fix for this is pretty easy, I can change NOP_Fixup to adjust
mnemonicendp, but now a bunch of tests start failing, we now produce
whitespace after the 'nop', which the tests don't expect.
So, I could update the tests to expect the whitespace....
...except I'm not a fan of trailing whitespace, so I'd really rather
not.
Turns out, I can pretty easily update the whitespace emitting code to
spot instructions that have zero operands and just not emit any
whitespace in this case. So this is what I've done.
I've left in the fix for NOP_Fixup, I think updating mnemonicendp is
probably a good thing, though this is not really required any more.
I've then updated all the tests that I saw failing to adjust the
expected patterns to account for the change in whitespace.
[1] https://sourceware.org/pipermail/binutils/2022-April/120610.html
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Requiring C99 means that uses of bfd_uint64_t can be replaced with
uint64_t, and similarly for bfd_int64_t, BFD_HOST_U_64_BIT, and
BFD_HOST_64_BIT. This patch does that, removes #ifdef BFD_HOST_*
and tidies a few places that print 64-bit values.
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As a preparatory step to allowing proper non-operand forms of specifying
embedded rounding / SAE, convert the internal representation to non-
operand form. While retaining properties (and in a few cases perhaps
providing more meaningful diagnostics), this means doing away with a few
hundred standalone templates, thus - as a nice side effect - reducing
memory consumption / cache occupancy.
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MASM doesn't consider {sae} and alike a separate operand; it is attached
to the last register operand instead, just like spelled out by the SDM.
Make the disassembler follow this first, before also adjusting the
assembler (such that it'll be easy to see that the assembler change
doesn't alter generated code).
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MASM doesn't support the {1to<n>} form; DWORD BCST (paralleling
DWORD PTR) and alike are to be used there instead. Make the disassembler
follow this first, before also adjusting the assembler (such that it'll
be easy to see that the assembler change doesn't alter generated code).
For VFPCLASSP{S,D,H} and vector conversions with shrinking element sizes
the original {1to<n>} operand suffix is retained, to disambiguate
output. I have no insight (yet) into how MASM expects those to be
disambiguated.
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Per Power ISA Version 3.1B 3.3.12, isel uses BC field rather than CRB
field present in binutils sources. Also, per 1.6.2, BC has the same
semantics as BA and BB fields, so this should keep the same flags and
mask, only with the different offset.
opcodes/
* ppc-opc.c
(BC): Define new field, with the same definition as CRB field,
but with the PPC_OPERAND_CR_BIT flag present.
gas/
* testsuite/gas/ppc/476.d: Update.
* testsuite/gas/ppc/a2.d: Update.
* testsuite/gas/ppc/e500.d: Update.
* testsuite/gas/ppc/power7.d: Update.
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With the upcoming SVP64 extension[0] to PowerPC architecture, it became
evident that PowerPC operand indices no longer fit 8 bits. This patch
switches the underlying type to uint16_t, also introducing a special
typedef so that any future extension goes even smoother.
[0] https://libre-soc.org
include/
* opcode/ppc.h (ppc_opindex_t): New typedef.
(struct powerpc_opcode): Use it.
(PPC_OPINDEX_MAX): Define.
gas/
* write.h (struct fix): Increase size of fx_pcrel_adjust.
Reorganise.
* config/tc-ppc.c (insn_validate): Use ppc_opindex_t for operands.
(md_assemble): Likewise.
(md_apply_fix): Likewise. Mask fx_pcrel_adjust with PPC_OPINDEX_MAX.
(ppc_setup_opcodes): Adjust opcode index assertion.
opcodes/
* ppc-dis.c (skip_optional_operands): Use ppc_opindex_t for
operand pointer.
(lookup_powerpc, lookup_prefix, lookup_vle, lookup_spe2): Likewise.
(print_insn_powerpc): Likewise.
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Update zfinx implement with zicsr, fix missing fcsr use by zfinx.
add zicsr imply by zfinx.
bfd/ChangeLog:
* elfxx-riscv.c: New imply.
gas/ChangeLog:
* testsuite/gas/riscv/csr-insns-pseudo-zfinx.d: New test.
opcodes/ChangeLog:
* riscv-opc.c: Update insn class.
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As fmv.x.q and fmv.q.x instructions are RV128-only (not RV64-only),
it should be removed until RV128 support for GNU Binutils is required
again.
gas/ChangeLog:
* testsuite/gas/riscv/fmv.x.q-rv64-fail.d: New failure test.
* testsuite/gas/riscv/fmv.x.q-rv64-fail.l: Likewise.
* testsuite/gas/riscv/fmv.x.q-rv64-fail.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_FMV_X_Q, MASK_FMV_X_Q,
MATCH_FMV_Q_X, MASK_FMV_Q_X): Remove RV128-only instructions.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Remove RV128-only instructions.
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It is only ever initialized from a boolean, so it as well as related
variables' types can simply be bool and there's no masking to 32 bits
needed in set_op().
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bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Added implicit f
and zicsr for zfh.
(riscv_supported_std_z_ext): Added default v1.0 version for zfh.
(riscv_multi_subset_supports): Handle INSN_CLASS_ZFH,
INSN_CLASS_D_AND_ZFH and INSN_CLASS_Q_AND_ZFH.
gas/
* config/tc-riscv.c (FLT_CHARS): Added "hH".
(macro): Expand Pseudo M_FLH and M_FSH.
(riscv_pseudo_table): Added .float16 directive.
* testsuite/gas/riscv/float16-be.d: New testcase for .float16.
* testsuite/gas/riscv/float16-le.d: Likewise.
* testsuite/gas/riscv/float16.s: Likewise.
* testsuite/gas/riscv/fp-zfh-insns.d: New testcase for zfh.
* testsuite/gas/riscv/fp-zfh-insns.s: Likewise.
include/
* opcode/riscv-opc.h: Added MASK and MATCH encodings for zfh.
* opcode/riscv.h: Added INSN_CLASS and pseudo macros for zfh.
opcodes/
* riscv-opc.c (riscv_opcodes): Added zfh instructions.
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As was done for hash_insn_array in commit d3d1cc7b13b4.
* cgen-dis.c (hash_insn_list): Increase size of buf. Assert
size is large enough.
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Note that opcodes is regenerated with cgen commit d1dd5fcc38e reverted,
due to failure of bpf to compile with that patch applied.
.../opcodes/bpf-opc.c:57:11: error: conversion from ‘long unsigned int’ to ‘unsigned int’ changes value from ‘18446744073709486335’ to ‘4294902015’ [-Werror=overflow]
57 | 64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
plus other similar errors.
cpu/
* mep.opc (print_tpreg, print_spreg): Delete unnecessary
forward declarations. Replace PTR with void *.
* mt.opc (print_dollarhex, print_pcrel): Delete forward decls.
opcodes/
* bpf-desc.c, * bpf-dis.c, * cris-desc.c,
* epiphany-desc.c, * epiphany-dis.c,
* fr30-desc.c, * fr30-dis.c, * frv-desc.c, * frv-dis.c,
* ip2k-desc.c, * ip2k-dis.c, * iq2000-desc.c, * iq2000-dis.c,
* lm32-desc.c, * lm32-dis.c, * m32c-desc.c, * m32c-dis.c,
* m32r-desc.c, * m32r-dis.c, * mep-desc.c, * mep-dis.c,
* mt-desc.c, * mt-dis.c, * or1k-desc.c, * or1k-dis.c,
* xc16x-desc.c, * xc16x-dis.c,
* xstormy16-desc.c, * xstormy16-dis.c: Regenerate.
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The non-cgen parts of opcodes.
* cr16-dis.c (print_arg): Replace PTR with void *.
* crx-dis.c (print_arg): Likewise.
* rl78-dis.c (print_insn_rl78_common): Don't use PTR cast.
* rx-dis.c (print_insn_rx): Likewise.
* visium-dis.c (print_insn_visium): Likewise.
* z8k-dis.c (print_insn_z8k): Likewise.
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Commit 39fb369834a3 "opcodes: Make i386-dis.c thread-safe" introduced
a number of casts to bfd_signed_vma that cause undefined behaviour
with a 32-bit libbfd. Revert those changes.
* i386-dis.c (OP_E_memory): Do not cast disp to bfd_signed_vma
for negation.
(get32, get32s): Don't use bfd_signed_vma here.
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TILE-Gx is a 64-bit core, so we should include those files in the
TARGET64_LIBOPCODES_CFILES as opposed to TARGET32_LIBOPCODES_CFILES.
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I believe it is a mistake to define ARCH_cris when BFD64 is defined. It is
a 32-bit architecture, so should be placed outside of the BFD64 block.
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opcodes/
* s390-opc.c (INSTR_RRF_R0RER): New instruction type.
(MASK_RRF_R0RER): Define mask for new instruction type.
* s390-opc.txt: Use RRF_R0RER for mgrk and RXY_RERRD for mg.
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Currently, the get_disassembler() implementations for riscv, csky, and
rl78--and mep_print_insn() for mep--access ELF variants of union fields
without first checking that the bfd actually represents an ELF. This
causes undefined behavior and crashes when disassembling non-ELF files
(the "binary" BFD, for example). Fix that.
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This also was mistakenly flagged as Evex.128.
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These were mistakenly flagged as Evex.128. Getting the LLIG status right
for insns allowing for SAE is a prereq for planned further work.
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Like VFPCLASSP{S,D} it has only a single operand allowing multiple
sizes, hence there are no pairs of operands to check for consistent
size.
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It's not just REX.W which is ignored with opcode 0x90. The same goes for
REX.R and REX.X as well as empty REX. None of these are forms of
"xchg %eax,%eax" (which would mean zero-extending %eax to %rax), so they
also shouldn't be disassembled this way.
While there simplify things: A single hook function suffices, thus
making it unnecessary to keep two expressions in sync. And checking
ins->address_mode for mode_64bit also is unnecessary, as "rex" can be
non-zero only in that case anyway.
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So far z16 was identified as arch14. After the machine has been
announced we can now add the real name.
gas/ChangeLog:
* config/tc-s390.c (s390_parse_cpu): Add z16 as alternate CPU
name.
* doc/as.texi: Add z16 and arch14 to CPU string list.
* doc/c-s390.texi: Add z16 to CPU string list.
opcodes/ChangeLog:
* s390-mkopc.c (main): Enable z16 as CPU string in the opcode
table.
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This commit adds partial support for disassembler styling in the i386
disassembler.
The i386 disassembler collects the instruction arguments into an array
of strings, and then loops over the array printing the arguments out
later on. The problem is that by the time we print the arguments out
it's not obvious what the type of each argument is.
Obviously this can be fixed, but I'd like to not do that as part of
this commit, rather, I'd prefer to keep this commit as small as
possible to get the basic infrastructure in place, then we can improve
on this, to add additional styling, in later commits.
For now then, I think this commit should correctly style mnemonics,
some immediates, and comments. Everything else will be printed as
plain text, which will include most instruction arguments, unless the
argument is printed as a symbol, by calling the print_address_func
callback.
Ignoring colours, there should be no other user visible changes in the
output of the disassembler in either objdump or gdb.
opcodes/ChangeLog:
* disassembler.c (disassemble_init_for_target): Set
created_styled_output for i386 based targets.
* i386-dis.c: Changed throughout to use fprintf_styled_func
instead of fprintf_func.
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Update the RISC-V disassembler to supply style information. This
allows objdump to apply syntax highlighting to the disassembler
output (when the appropriate command line flag is used).
Ignoring colours, there should be no other user visible changes in the
output of the disassembler in either objdump or gdb.
opcodes/ChangeLog:
* disassembler.c (disassemble_init_for_target): Set
created_styled_output for riscv.
* riscv-dis.c: Changed throughout to use fprintf_styled_func
instead of fprintf_func.
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This commit adds the _option_ of having disassembler output syntax
highlighted in objdump. This option is _off_ by default. The new
command line options are:
--disassembler-color=off # The default.
--disassembler-color=color
--disassembler-color=extended-color
I have implemented two colour modes, using the same option names as we
use of --visualize-jumps, a basic 8-color mode ("color"), and an
extended 8bit color mode ("extended-color").
The syntax highlighting requires that each targets disassembler be
updated; each time the disassembler produces some output we now pass
through an additional parameter indicating what style should be
applied to the text.
As updating all target disassemblers is a large task, the old API is
maintained. And so, a user of the disassembler (i.e. objdump, gdb)
must provide two functions, the current non-styled print function, and
a new, styled print function.
I don't currently have a plan for converting every single target
disassembler, my hope is that interested folk will update the
disassemblers they are interested in. But it is possible some might
never get updated.
In this initial series I intend to convert the RISC-V disassembler
completely, and also do a partial conversion of the x86 disassembler.
Hopefully having the x86 disassembler at least partial converted will
allow more people to try this out easily and provide feedback.
In this commit I have focused on objdump. The changes to GDB at this
point are the bare minimum required to get things compiling, GDB makes
no use of the styling information to provide any colors, that will
come later, if this commit is accepted.
This first commit in the series doesn't convert any target
disassemblers at all (the next two commits will update some targets),
so after this commit, the only color you will see in the disassembler
output, is that produced from objdump itself, e.g. from
objdump_print_addr_with_sym, where we print an address and a symbol
name, these are now printed with styling information, and so will have
colors applied (if the option is on).
Finally, my ability to pick "good" colors is ... well, terrible. I'm
in no way committed to the colors I've picked here, so I encourage
people to suggest new colors, or wait for this commit to land, and
then patch the choice of colors.
I do have an idea about using possibly an environment variable to
allow the objdump colors to be customised, but I haven't done anything
like that in this commit, the color choices are just fixed in the code
for now.
binutils/ChangeLog:
* NEWS: Mention new feature.
* doc/binutils.texi (objdump): Describe --disassembler-color
option.
* objdump.c (disassembler_color): New global.
(disassembler_extended_color): Likewise.
(disassembler_in_comment): Likewise.
(usage): Mention --disassembler-color option.
(long_options): Add --disassembler-color option.
(objdump_print_value): Use fprintf_styled_func instead of
fprintf_func.
(objdump_print_symname): Likewise.
(objdump_print_addr_with_sym): Likewise.
(objdump_color_for_disassembler_style): New function.
(objdump_styled_sprintf): New function.
(fprintf_styled): New function.
(disassemble_jumps): Use disassemble_set_printf, and reset
disassembler_in_comment.
(null_styled_print): New function.
(disassemble_bytes): Use disassemble_set_printf, and reset
disassembler_in_comment.
(disassemble_data): Update init_disassemble_info call.
(main): Handle --disassembler-color option.
include/ChangeLog:
* dis-asm.h (enum disassembler_style): New enum.
(struct disassemble_info): Add fprintf_styled_func field, and
created_styled_output field.
(disassemble_set_printf): Declare.
(init_disassemble_info): Add additional parameter.
(INIT_DISASSEMBLE_INFO): Add additional parameter.
opcodes/ChangeLog:
* dis-init.c (init_disassemble_info): Take extra parameter,
initialize the new fprintf_styled_func and created_styled_output
fields.
* disassembler.c (disassemble_set_printf): New function definition.
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Remove bfd_arch_l1om and bfd_arch_k1om since L1OM/K1OM support has been
removed from gas, ld and opcodes.
bfd/
* Makefile.am (ALL_MACHINES): Remove cpu-l1om.lo and cpu-k1om.lo.
(ALL_MACHINES_CFILES): Remove cpu-l1om.c and cpu-k1om.c.
* archures.c (bfd_mach_l1om): Removed.
(bfd_mach_l1om_intel_syntax): Likewise.
(bfd_mach_k1om): Likewise.
(bfd_mach_k1om_intel_syntax): Likewise.
(bfd_k1om_arch): Likewise.
(bfd_l1om_arch): Likewise.
(bfd_archures_list): Remove bfd_k1om_arch and bfd_l1om_arch
references.
* config.bfd (targ_selvecs): Remove l1om_elf64_vec.
l1om_elf64_fbsd_vec, k1om_elf64_vec and k1om_elf64_fbsd_vec.
(targ_archs): Remove bfd_l1om_arch and bfd_k1om_arch.
* configure.ac (k1om_elf64_vec): Removed.
(k1om_elf64_fbsd_vec): Likewise.
(l1om_elf64_vec): Likewise.
(l1om_elf64_fbsd_vec): Likewise.
* cpu-k1om.c: Removed.
* cpu-l1om.c: Likewise.
* elf64-x86-64.c (elf64_l1om_elf_object_p): Removed.
(elf64_k1om_elf_object_p): Likewise.
(l1om_elf64_vec): Removed.
(l1om_elf64_fbsd_vec): Likewise.
(k1om_elf64_vec): Likewise.
(k1om_elf64_fbsd_vec): Likewise.
(ELF_TARGET_OS): Undefine.
* targets.c (_bfd_target_vector): Remove k1om_elf64_vec,
k1om_elf64_fbsd_vec, l1om_elf64_vec and l1om_elf64_fbsd_vec.
* Makefile.in: Regenerate.
* bfd-in2.h: Likewise.
* configure: Likewise.
opcodes/
* configure.ac: Remove bfd_arch_l1om/bfd_arch_k1om references.
* disassemble.c (disassembler): Likewise.
* configure: Regenerate.
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FEAT_RNG is an optional Armv8.5-A extension, but it can be backported
to earlier architectures as well. GAS previously made the RNG registers
conditional on having both armv8.5-a and +rng, but only +rng should be
required.
This seems to be the only feature that was handled like this.
opcodes/
* aarch64-opc.c (SR_RNG): Don't require V8_5.
gas/
* testsuite/gas/aarch64/rng-1.s, testsuite/gas/aarch64/rng-1.d: New
test.
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While the spec isn't explicit about this, it pointing out the similarity
with the D extension ought to extend to the ignoring of a meaningless
rounding mode: "Note FCVT.D.W[U] always produces an exact result and is
unaffected by rounding mode." Hence the chosen encodings also ought to
match.
Note that to avoid breaking existing code the forms with a 3rd operand
are not removed, which means there continues to be a difference to
FCVT.D.W[U].
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My previous nm patch handled all cases but one -- if the user set NM in
the environment to a path which contained an option, libtool's nm
detection tries to run nm against a copy of nm with the options in it:
e.g. if NM was set to "nm --blargle", and nm was found in /usr/bin, the
test would try to run "/usr/bin/nm --blargle /usr/bin/nm --blargle".
This is unlikely to be desirable: in this case we should run
"/usr/bin/nm --blargle /usr/bin/nm".
Furthermore, as part of this nm has to detect when the passed-in $NM
contains a path, and in that case avoid doing a path search itself.
This too was thrown off if an option contained something that looked
like a path, e.g. NM="nm -B../prev-gcc"; libtool then tries to run
"nm -B../prev-gcc nm" which rarely works well (and indeed it looks
to see whether that nm exists, finds it doesn't, and wrongly concludes
that nm -p or whatever does not work).
Fix all of these by clipping all options (defined as everything
including and after the first " -") before deciding whether nm
contains a path (but not using the clipped value for anything else),
and then removing all options from the path-modified nm before
looking to see whether that nm existed.
NM=my-nm now does a path search and runs e.g.
/usr/bin/my-nm -B /usr/bin/my-nm
NM=/usr/bin/my-nm now avoids a path search and runs e.g.
/usr/bin/my-nm -B /usr/bin/my-nm
NM="my-nm -p../wombat" now does a path search and runs e.g.
/usr/bin/my-nm -p../wombat -B /usr/bin/my-nm
NM="../prev-binutils/new-nm -B../prev-gcc" now avoids a path search:
../prev-binutils/my-nm -B../prev-gcc -B ../prev-binutils/my-nm
This seems to be all combinations, including those used by GCC bootstrap
(which, before this commit, fails to bootstrap when configured
--with-build-config=bootstrap-lto, because the lto plugin is now using
--export-symbols-regex, which requires libtool to find a working nm,
while also using -B../prev-gcc to point at the lto plugin associated
with the GCC just built.)
Regenerate all affected configure scripts.
* libtool.m4 (LT_PATH_NM): Handle user-specified NM with
options, including options containing paths.
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There wasn't any real support anyway: None of the sub-architecture
specific insns were ever supported.
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Change "char buffer[8192];" into "char *buffer =
(char *) malloc(1000 + 6 * len_str);" in function
loongarch_expand_macro_with_format_map.
gas/
* config/tc-loongarch.c
include/
* opcode/loongarch.h
opcodes/
* loongarch-coder.c
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opcodes/
* loongarch-coder.c :
int32_t ret = 0;
ret <<= sizeof (ret) * 8 - len;
ret >>= sizeof (ret) * 8 - len;
...
Avoid ubsan warning.
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By slightly relaxing the checking in operand_type_register_match() we
can fold the vector shift insns with an XMM source as well. While
strictly speaking an overlap in just one size (see the code comment) is
not enough (both operands could have multiple sizes with just a single
common one), this is good enough for all templates we have, or which
could sensibly / usefully appear (within the scope of the present
operand matching model).
Tightening this a little would be possible, but would require broadcast
related information to be passed into the function.
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They have only a single operand allowing multiple sizes, hence there are
no pairs of operands to check for consistent size.
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Like for AVX512VL we can make the handling of operand sizes a little
more flexible to allow reducing the number of templates we have.
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This commit adds 'Zicbom' / 'Zicboz' instructions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
new instruction classes.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN,
MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL,
MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add cache-block management
instructions.
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This commit adds 'Zicbop' hint instructions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
new instruction class.
gas/ChangeLog:
* config/tc-riscv.c (riscv_ip): Add handling for new operand
type 'f' (32-byte aligned pseudo S-type immediate for prefetch
hints).
(validate_riscv_insn): Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I,
MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W,
MASK_PREFETCH_W): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
class INSN_CLASS_ZICBOP.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add handling for new operand
type.
* riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.
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Setting this field risks cpu_flags_all_zero() mistakenly returning
"false" when the object passed in was e.g. the result of ANDing together
two objects which had the bit set, or ANDNing together an object with
the field set and one with the field clear.
While there also avoid setting CpuNo64: Like Cpu64 this is driven
differently anyway and hence shouldn't be set anywhere by default.
Note that the moving of the two items in i386-gen.c's cpu_flags[] is
only for documentation purposes (and slight reducing of overhead), as
the fields are sorted anyway upon program start.
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There's no need for the arbitrary special "unknown" token: Simply
recognize the leading ~ and process everything else the same, merely
recording whether to set individual fields to 1 or 0.
While there exclude CpuIAMCU from CPU_UNKNOWN_FLAGS - CPU_IAMCU_FLAGS
override cpu_arch_flags anyway when -march=iamcu is passed, and there's
no reason to have the stray flag set even if no insn actually is keyed
to it.
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