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2021-07-14x86: Add int1 as one byte opcode 0xf1H.J. Lu3-1/+15
2021-07-07Add changelog entries for last commitAndreas Krebbel1-0/+4
2021-07-07IBM Z: Add another arch14 instructionAndreas Krebbel1-0/+2
2021-07-05Updated translations (mainly Ukranian and French) triggered by creation of 2....Nick Clifton3-709/+868
2021-07-03Update version number and regenerate filesNick Clifton3-220/+254
2021-07-03Add markers for 2.37 branchNick Clifton1-0/+4
2021-07-02Re: Fix minor NDS32 renaming snafuAlan Modra3-12/+21
2021-07-01cgen: split GUILE setting outMike Frysinger3-2/+10
2021-07-01opcodes: constify & local meps macrosMike Frysinger2-5/+12
2021-07-01opcodes: cleanup nds32 variablesMike Frysinger3-40/+57
2021-07-01opcodes: constify & localize z80 opcodesMike Frysinger2-2/+7
2021-07-01opcodes: constify & scope microblaze opcodesMike Frysinger3-11/+23
2021-07-01opcodes: constify aarch64_opcode_tablesMike Frysinger3-3/+8
2021-06-22opcodes: make use of __builtin_popcount when availableAndrew Burgess2-0/+9
2021-06-22picojava assembler and disassembler fixesAlan Modra2-2/+8
2021-06-19ubsan: vax: pointer overflowAlan Modra2-1/+5
2021-06-19Fix another strncpy warningAlan Modra2-1/+6
2021-06-17powerpc: move cell "or rx,rx,rx" hintsAlan Modra2-5/+10
2021-06-03PR1202, mcore disassembler: wrong address looptAlan Modra2-4/+10
2021-06-02arc: Construct disassembler options dynamicallyShahab Vahedi2-27/+161
2021-05-29PowerPC table driven -Mraw disassemblyAlan Modra3-1635/+1634
2021-05-29MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructionsMaciej W. Rozycki2-66/+73
2021-05-29MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membershipMaciej W. Rozycki2-51/+61
2021-05-29MIPS/opcodes: Remove DMFC3 and DMTC3 instructionsMaciej W. Rozycki2-4/+5
2021-05-29MIPS/opcodes: Disassemble the RFE instructionMaciej W. Rozycki2-2/+8
2021-05-29MIPS/opcodes: Add legacy CP1 control register namesMaciej W. Rozycki2-25/+47
2021-05-29MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki4-17/+39
2021-05-29MIPS/opcodes: Add TX39 CP0 register namesMaciej W. Rozycki2-1/+19
2021-05-29MIPS/opcodes: Free up redundant `g' operand codeMaciej W. Rozycki2-4/+9
2021-05-29microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1Maciej W. Rozycki2-1/+6
2021-05-27PowerPC: Add new xxmr and xxlnot extended mnemonicsPeter Bergner2-0/+6
2021-05-25Regen cris filesAlan Modra5-30/+67
2021-05-24opcodes: cris: move desc & opc files from sim/Mike Frysinger9-4/+3403
2021-05-18RISC-V: PR27814, Objdump crashes when disassembling a non-ELF RISC-V binary.Job Noorman2-10/+20
2021-05-17arm: Fix bugs with MVE vmov from two GPRs to vector lanesAlex Coplan2-2/+14
2021-05-11Fix an illegal memory access when attempting to disassemble a corrupt TIC30 b...Nick Clifton2-0/+9
2021-05-06or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha()Stafford Horne2-1/+11
2021-05-01opcodes: xtensa: support branch visualizationMax Filippov2-0/+15
2021-04-26x86: optimize LEAJan Beulich3-2/+7
2021-04-23opcodes: xtensa: display loaded literal valueMax Filippov2-1/+24
2021-04-23opcodes: xtensa: improve literal outputMax Filippov2-0/+6
2021-04-19aarch64: New instructions for maintenance of GPT entries cached in a TLBPrzemyslaw Wirkus2-0/+10
2021-04-19aarch64: Add new data cache maintenance operationsPrzemyslaw Wirkus2-0/+7
2021-04-19arm64: add two initializersJan Beulich2-2/+8
2021-04-16aarch64: Define RME system registersPrzemyslaw Wirkus2-0/+8
2021-04-16Update the ChangeLog, and add the missing entries.Nelson Chu1-0/+5
2021-04-16RISC-V: compress "addi d,CV,z" to "c.mv d,CV"Lifang Xia1-0/+1
2021-04-13ENABLE_CHECKING in bfd, opcodes, binutils, ldAlan Modra4-2/+42
2021-04-09AArch64: Fix Atomic LD64/ST64 classification.Tejas Belagod2-4/+9
2021-04-09PowerPC disassembly of pcrel referencesAlan Modra2-10/+143
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