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2020-11-09Add support for the LMBD (left-most bit detect) instruction to the PRU assemb...Spencer E. Olson2-0/+7
2020-11-09aarch64: Update LS64 feature with system registerPrzemyslaw Wirkus2-0/+6
2020-11-09aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus6-168/+183
2020-11-06aarch64: Extract Pointer Authentication feature from Armv8.3-APrzemyslaw Wirkus2-33/+45
2020-11-04aarch64: Update feature RAS system registersPrzemyslaw Wirkus2-0/+10
2020-11-03[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus5-2181/+2249
2020-11-03[PATCH] aarch64: Update missing ChangeLog for AArch64 commitsPrzemyslaw Wirkus1-0/+54
2020-10-30[PATCH][GAS] aarch64: Add WFIT instruction for Armv8.7-aPrzemyslaw Wirkus4-1347/+1353
2020-10-28aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus5-1417/+1430
2020-10-28aarch64: Add WFET instruction for Armv8.7-aPrzemyslaw Wirkus4-1347/+1353
2020-10-28aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus10-1455/+1513
2020-10-28aarch64: Add basic support for armv8.7-a architecturePrzemyslaw Wirkus1-0/+3
2020-10-26CSKY: Change plsl.u16 to plsl.16.Cooper Qu2-1/+5
2020-10-26CSKY: Fix and add some instructions for VDSPV1.Cooper Qu3-39/+231
2020-10-26Change avxvnni disassembler output from {vex3} to {vex}Cui,Lili2-1/+4
2020-10-22[PATCH][GAS][AArch64] Define BRBE system registersPrzemyslaw Wirkus1-0/+106
2020-10-22aarch64: Define CSRE system registersPrzemyslaw Wirkus1-0/+13
2020-10-22opcodes/po/es.po: Remove the duplicated entryH.J. Lu2-8/+4
2020-10-22Fix printf formatting errors where "0x" is used as a prefix for a decimal num...Dr. David Alan Gilbert2-2/+6
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian7-4213/+4494
2020-10-16Enhancement for avx-vnni patchCui,Lili6-11428/+11439
2020-10-14x86: Support Intel AVX VNNIH.J. Lu7-4539/+4705
2020-10-14x86: Add support for Intel HRESET instructionLili Cui7-4467/+4558
2020-10-14x86: Support Intel UINTRLili Cui7-4203/+8587
2020-10-14x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu4-1077/+1136
2020-10-13x86: Rename VexOpcode to OpcodePrefixH.J. Lu5-2149/+2180
2020-10-05Fix spelling mistakesSamanta Navarro4-5/+11
2020-10-05x86-64: Always display suffix for %LQ in 64bitH.J. Lu2-1/+6
2020-10-05x86: Clear modrm if not neededH.J. Lu2-4/+15
2020-09-28This patch introduces ETMv4 (Embedded Trace Macrocell) system registers for t...Przemyslaw Wirkus2-3/+236
2020-09-28This patch introduces ETE (Embedded Trace Extension) system registers for the...Przemyslaw Wirkus2-0/+10
2020-09-28This patch introduces TRBE (Trace Buffer Extension) system registers for the ...Przemyslaw Wirkus2-0/+13
2020-09-26ubsan: opcodes/csky-opc.h:929 shift exponent 536870912Alan Modra3-28/+34
2020-09-25Put together MOD_VEX_0F38* in i386-dis.c,Cui,Lili2-62/+67
2020-09-24csky/opcodes: enclose if body in curly bracesAndrew Burgess2-2/+9
2020-09-24Add support for Intel TDX instructions.Cui,Lili7-4266/+4422
2020-09-23CSKY: Add objdump option -M abi-names.Cooper Qu3-180/+531
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo7-4183/+4507
2020-09-21rx-dis.c:103:3: suspicious concatenation of string literalsAlan Modra2-8/+16
2020-09-18bpf: xBPF SDIV, SMOD instructionsDavid Faust5-6/+194
2020-09-17opcodes/csky: return the default disassembler when there is no bfdAndrew Burgess2-15/+22
2020-09-16Tidy elf_symbol_fromAlan Modra2-1/+5
2020-09-10Stop symbols generated by the annobin gcc plugin from breaking the disassembl...Nick Clifton2-0/+31
2020-09-10CSKY: Add L2Cache instructions for CK860.Cooper Qu2-109/+124
2020-09-10CSKY: Add new arches while refine the cpu option process.Cooper Qu1-0/+2
2020-09-10Fix compile time warnings when building for the CSKY target on a 32-bit host.Nick Clifton2-1/+6
2020-09-10sprintf arg overlaps destinationAlan Modra2-4/+8
2020-09-09CSKY: Change mvtc and mulsw's ISA flag.Cooper Qu2-2/+7
2020-09-09CSKY: Add FPUV3 instructions, which supported by ck860f.Cooper Qu3-2/+2133
2020-09-08aarch64: Add support for Armv8-R system registersAlex Coplan3-10/+93
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