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| author | Cooper Qu <cooper.qu@linux.alibaba.com> | 2020-09-07 17:25:14 +0800 |
|---|---|---|
| committer | Lifang Xia <lifang_xia@c-sky.com> | 2020-09-09 19:26:34 +0800 |
| commit | 6a1ed9106f4f937eddc194915d6e3ec4ecc79f20 (patch) | |
| tree | d9fdf754703e4e0d810f0a4562ee803ec85a7180 /opcodes | |
| parent | a2061b9f29ea1ae8d40d5627bb8e704fa9e95a67 (diff) | |
| download | gdb-6a1ed9106f4f937eddc194915d6e3ec4ecc79f20.zip gdb-6a1ed9106f4f937eddc194915d6e3ec4ecc79f20.tar.gz gdb-6a1ed9106f4f937eddc194915d6e3ec4ecc79f20.tar.bz2 | |
CSKY: Change mvtc and mulsw's ISA flag.
gas/
* config/tc-csky.c (CSKYV2_ISA_DSP): CSKY_ISA_DSPE60.
(CSKY_ISA_860): Likewise.
include/
* opcode/csky.h (CSKY_ISA_DSPE60): Define.
opcodes/
* csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
ISA flag.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/csky-opc.h | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4f416bf..bd5a284 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com> + * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's + ISA flag. + +2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com> + * csky-dis.c (csky_output_operand): Add handlers for OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH diff --git a/opcodes/csky-opc.h b/opcodes/csky-opc.h index fac30ae..5a6068c 100644 --- a/opcodes/csky-opc.h +++ b/opcodes/csky-opc.h @@ -2687,7 +2687,7 @@ const struct csky_opcode csky_v2_opcodes[] = CSKY_ISA_DSP), OP32 ("mvtc", OPCODE_INFO0 (0xc4009a00), - CSKY_ISA_DSP), + CSKY_ISA_DSPE60), OP32 ("mfhi", OPCODE_INFO1 (0xc4009c20, (0_4, AREG, OPRND_SHIFT_0_BIT)), @@ -4119,7 +4119,7 @@ const struct csky_opcode csky_v2_opcodes[] = OPCODE_INFO2 (0xc4009420, (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), (21_25, AREG, OPRND_SHIFT_0_BIT)), - CSKY_ISA_DSP), + CSKY_ISA_DSPE60), OP16_OP32 ("ld.b", SOPCODE_INFO2 (0x8000, (5_7, GREG0_7, OPRND_SHIFT_0_BIT), |