| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-07-27 | Support Intel PBNDKB | Hu, Lin1 | 7 | -6040/+6090 |
| 2023-07-27 | Support Intel SM4 | Haochen Jiang | 7 | -6751/+6825 |
| 2023-07-27 | Support Intel SM3 | Haochen Jiang | 7 | -6974/+7105 |
| 2023-07-27 | Support Intel SHA512 | Haochen Jiang | 7 | -7051/+7206 |
| 2023-07-27 | Support Intel AVX-VNNI-INT16 | konglin1 | 7 | -5622/+9878 |
| 2023-07-26 | bpf: fix register NEG[32] instructions | Jose E. Marchesi | 2 | -2/+7 |
| 2023-07-26 | Regen bpf opcodes POTFILE | Alan Modra | 3 | -7/+2 |
| 2023-07-25 | bpf: Add atomic compare-and-exchange instructions | David Faust | 1 | -0/+12 |
| 2023-07-25 | bpf: Update atomic instruction pseudo-C syntax | David Faust | 1 | -16/+16 |
| 2023-07-24 | Updated translations for bfd, gold and opcodes | Nick Clifton | 1 | -372/+341 |
| 2023-07-24 | bpf: gas,include,opcode: add suppor for instructions BSWAP{16,32,64} | Jose E. Marchesi | 2 | -0/+13 |
| 2023-07-24 | bpf: gas,opcodes: fix pseudoc syntax for MOVS* and LDXS* insns | Jose E. Marchesi | 2 | -10/+15 |
| 2023-07-24 | bpf: add support for jal/gotol jump instruction with 32-bit target | Jose E. Marchesi | 2 | -0/+8 |
| 2023-07-21 | bpf: disasemble offsets of value 0 as "+0" | David Faust | 1 | -2/+2 |
| 2023-07-21 | bpf: opcodes, gas: support for signed load V4 instructions | Jose E. Marchesi | 2 | -0/+15 |
| 2023-07-21 | bpf: opcodes, gas: support for signed register move V4 instructions | Jose E. Marchesi | 2 | -0/+17 |
| 2023-07-21 | bpf: add missing bpf-dis.c to opcodes/Makefile.am | Jose E. Marchesi | 3 | -0/+8 |
| 2023-07-21 | DesCGENization of the BPF binutils port | Jose E. Marchesi | 12 | -6380/+680 |
| 2023-07-21 | x86: adjust disassembly of insns operating on selector values | Jan Beulich | 1 | -6/+6 |
| 2023-07-21 | x86: simplify disassembly of LAR/LSL | Jan Beulich | 1 | -14/+2 |
| 2023-07-19 | Updated Romainian translation for the opcodes directory | Nick Clifton | 1 | -374/+344 |
| 2023-07-18 | RISC-V: Supports Zcb extension. | Jiawei | 2 | -0/+42 |
| 2023-07-14 | Fix loongarch build with gcc-4.5 | Alan Modra | 1 | -1/+1 |
| 2023-07-11 | x86: simplify table-referencing macros | Jan Beulich | 1 | -17/+15 |
| 2023-07-11 | x86: convert 0FXOP to just XOP in enumerator names | Jan Beulich | 1 | -304/+304 |
| 2023-07-11 | x86: misc further register-only insns don't need to go through mod_table[] | Jan Beulich | 4 | -163/+77 |
| 2023-07-11 | x86: various operations on mask registers can avoid going through mod_table[] | Jan Beulich | 4 | -296/+176 |
| 2023-07-11 | x86: slightly rework handling of some register-only insns | Jan Beulich | 2 | -62/+53 |
| 2023-07-11 | x86: SIMD shift-by-immediate don't need to go through mod_table[] | Jan Beulich | 1 | -54/+18 |
| 2023-07-11 | x86: misc further memory-only insns don't need to go through mod_table[] | Jan Beulich | 6 | -315/+124 |
| 2023-07-11 | x86: {,V}MOVNT* don't need to go through mod_table[] | Jan Beulich | 3 | -64/+18 |
| 2023-07-11 | x86: fold legacy/VEX {,V}MOV{H,L}* entries | Jan Beulich | 2 | -68/+34 |
| 2023-07-11 | x86: fold certain legacy/VEX table entries | Jan Beulich | 2 | -305/+109 |
| 2023-07-04 | x86: optimize 128-bit VPBROADCASTQ to VPUNPCKLQDQ | Jan Beulich | 2 | -3/+3 |
| 2023-07-04 | x86: optimize pre-AVX512 {,V}PCMPGT* with identical sources | Jan Beulich | 2 | -21/+21 |
| 2023-07-04 | x86: optimize pre-AVX512 {,V}PCMPEQQ with identical sources | Jan Beulich | 2 | -5/+5 |
| 2023-07-04 | x86: flag bad EVEX masking for miscellaneous insns | Jan Beulich | 6 | -44/+51 |
| 2023-07-04 | x86: flag EVEX masking when destination is GPR(-like) | Jan Beulich | 1 | -1/+16 |
| 2023-07-04 | x86: flag EVEX.z set when destination is memory | Jan Beulich | 1 | -0/+7 |
| 2023-07-04 | x86: flag EVEX.z set when destination is a mask register | Jan Beulich | 1 | -0/+12 |
| 2023-07-04 | x86: re-work EVEX-z-without-masking check | Jan Beulich | 1 | -10/+8 |
| 2023-07-04 | Updated Ukranian, Romanian and German translations for various sub-directories | Nick Clifton | 2 | -747/+679 |
| 2023-07-04 | arc: Update neg<.f> 0,b encoding | Claudiu Zissulescu | 1 | -1/+1 |
| 2023-07-03 | Change version number to 2.41.50 and regenerate files | Nick Clifton | 3 | -375/+211 |
| 2023-07-03 | Add markers for the 2.41 branch | Nick Clifton | 1 | -0/+4 |
| 2023-07-03 | opcodes/loongarch: Mark address offset operands of LVZ/LBT insns as such | WANG Xuerui | 1 | -28/+28 |
| 2023-07-01 | RISC-V: Add support for the Zvksh ISA extension | Christoph Müllner | 1 | -0/+4 |
| 2023-07-01 | RISC-V: Add support for the Zvksed ISA extension | Christoph Müllner | 1 | -0/+5 |
| 2023-07-01 | RISC-V: Add support for the Zvknh[a,b] ISA extensions | Christoph Müllner | 1 | -0/+5 |
| 2023-07-01 | RISC-V: Add support for the Zvkned ISA extension | Christoph Müllner | 1 | -0/+13 |
