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path: root/opcodes/riscv-opc.c
AgeCommit message (Expand)AuthorFilesLines
2023-11-07RISC-V: Add support for XCValu extension in CV32E40PMary Bennett1-0/+35
2023-11-07RISC-V: Add support for XCVmac extension in CV32E40PMary Bennett1-0/+26
2023-11-03RISC-V: reduce redundancy in load/store macro insn handlingJan Beulich1-19/+19
2023-09-07RISC-V: Clarify the naming rules of vendor operands.Nelson Chu1-65/+65
2023-09-05RISC-V: fold duplicate code in vector_macro()Jan Beulich1-2/+2
2023-09-01RISC-V: move various alias entriesJan Beulich1-35/+35
2023-08-30RISC-V: Make XVentanaCondOps RV64 onlyTsukasa OI1-2/+2
2023-08-15RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa'Tsukasa OI1-1/+1
2023-08-15RISC-V: Add support for the 'Zihintntl' extensionTsukasa OI1-0/+12
2023-08-15RISC-V: remove indirection from register tablesJan Beulich1-6/+6
2023-08-11RISC-V: Fix opcode entries of "vmsge{,u}.vx"Tsukasa OI1-4/+4
2023-08-07RISC-V: move comment describing rules for riscv_opcodes[]Jan Beulich1-10/+10
2023-08-02Revert "2.41 Release sources"Sam James1-0/+28
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton1-28/+0
2023-07-18RISC-V: Supports Zcb extension.Jiawei1-0/+28
2023-07-01RISC-V: Add support for the Zvksh ISA extensionChristoph Müllner1-0/+4
2023-07-01RISC-V: Add support for the Zvksed ISA extensionChristoph Müllner1-0/+5
2023-07-01RISC-V: Add support for the Zvknh[a,b] ISA extensionsChristoph Müllner1-0/+5
2023-07-01RISC-V: Add support for the Zvkned ISA extensionChristoph Müllner1-0/+13
2023-07-01RISC-V: Add support for the Zvkg ISA extensionChristoph Müllner1-0/+4
2023-07-01RISC-V: Add support for the Zvbc extensionNathan Huckleberry1-0/+6
2023-07-01RISC-V: Add support for the Zvbb ISA extensionChristoph Müllner1-0/+18
2023-06-30RISC-V: Add support for the Zfa extensionChristoph Müllner1-0/+64
2023-06-27 RISC-V: Support Zicond extensionPhilipp Tomsich1-0/+4
2023-06-01RISC-V: PR30449, Add lga assembler macro support.Jim Wilson1-0/+1
2023-04-26 RISC-V: Support XVentanaCondOps extensionPhilipp Tomsich1-0/+4
2023-03-31RISC-V: Allocate "various" operand typeTsukasa OI1-3/+3
2023-01-31RISC-V: make C-extension JAL available again for (32-bit) assemblyJan Beulich1-1/+1
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2022-11-17RISC-V: Add T-Head Int vendor extensionChristoph Müllner1-0/+4
2022-11-17RISC-V: Add T-Head Fmv vendor extensionChristoph Müllner1-0/+4
2022-11-09RISC-V: xtheadfmemidx: Use fp register in mnemonicsChristoph Müllner1-8/+8
2022-10-14RISC-V: Move standard hints before all instructionsTsukasa OI1-4/+8
2022-10-14RISC-V: Move certain arrays to riscv-opc.cTsukasa OI1-0/+13
2022-10-04RISC-V: Renamed INSN_CLASS for floating point in integer extensions.Nelson Chu1-222/+222
2022-10-03RISC-V: Move supervisor instructions after all unprivileged onesTsukasa OI1-32/+32
2022-09-30RISC-V: Relax "fmv.[sdq]" requirementsTsukasa OI1-3/+3
2022-09-30RISC-V: drop stray INSN_ALIAS flagsJan Beulich1-3/+3
2022-09-30RISC-V: re-arrange opcode table for consistent alias handlingJan Beulich1-38/+38
2022-09-23RISC-V: Add Zawrs ISA extension supportChristoph Müllner1-0/+4
2022-09-22RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner1-0/+24
2022-09-22RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner1-0/+60
2022-09-22RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner1-0/+10
2022-09-22RISC-V: Add T-Head MAC vendor extensionChristoph Müllner1-0/+8
2022-09-22RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner1-0/+4
2022-09-22RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner1-0/+17
2022-09-22RISC-V: Add T-Head SYNC vendor extensionChristoph Müllner1-0/+7
2022-09-22RISC-V: Add T-Head CMO vendor extensionChristoph Müllner1-0/+25
2022-08-30RISC-V: Add 'Zmmul' extension in assembler.Tsukasa OI1-13/+13
2022-07-07RISC-V: Added Zfhmin and Zhinxmin.Tsukasa OI1-63/+63