riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
6 days	RISC-V: avoid use of match_opcode() in riscv_insn_types[]	Jan Beulich	1	-102/+102
13 days	RISC-V: Add Zabha extension CAS instructions.	Jiawei	1	-0/+8
2024-06-18	RISC-V: Add SiFive cease extension v1.0	Hau Hsu	1	-0/+3
2024-06-18	RISC-V: Support Zacas extension.	Gianluca Guida	1	-0/+26
2024-06-06	RISC-V: Add support for Zvfbfwma extension	Xiao Zeng	1	-0/+4
2024-06-06	RISC-V: Add support for Zvfbfmin extension	Xiao Zeng	1	-0/+4
2024-06-06	RISC-V: Add support for Zfbfmin extension	Xiao Zeng	1	-0/+5
2024-06-05	RISC-V: Add support for XCVmem extension in CV32E40P	Mary Bennett	1	-0/+26
2024-06-05	RISC-V: Add support for XCVbi extension in CV32E40P	Mary Bennett	1	-0/+4
2024-06-05	RISC-V: Add support for XCVelw extension in CV32E40P	Mary Bennett	1	-0/+3
2024-05-08	RISC-V: Support B, Zaamo and Zalrsc extensions.	Nelson Chu	1	-88/+88
2024-04-09	RISC-V: Support Zcmp push/pop instructions.	Jiawei	1	-0/+20
2024-03-08	RISC-V: Support Zabha extension.	Jiawei	1	-0/+74
2024-02-29	RISC-V: Add assembly support for TLSDESC.	Tatsuyuki Ishi	1	-0/+1
2024-01-05	RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvli	Jin Ma	1	-1/+13
2024-01-04	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2023-12-29	RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extension	Jin Ma	1	-0/+5
2023-12-14	RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.	Jin Ma	1	-1/+1
2023-12-01	RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0	Nelson Chu	1	-0/+30
2023-12-01	RISC-V: Zv*: Add support for Zvkb ISA extension	Christoph Müllner	1	-10/+10
2023-11-24	RISC-V: drop leftover match_never() references	Jan Beulich	1	-4/+4
2023-11-24	RISC-V: reduce redundancy in sign/zero extension macro insn handling	Jan Beulich	1	-2/+2
2023-11-24	RISC-V: disallow x0 with certain macro-insns	Jan Beulich	1	-45/+45
2023-11-23	RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+15
2023-11-23	RISC-V: Add vector mask instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+19
2023-11-23	RISC-V: Add reductions instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+16
2023-11-23	RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor e...	Jin Ma	1	-0/+86
2023-11-23	RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor exte...	Jin Ma	1	-0/+36
2023-11-23	RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+143
2023-11-23	RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extension	Jin Ma	1	-0/+18
2023-11-23	RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+280
2023-11-23	RISC-V: Add load/store instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+44
2023-11-23	RISC-V: Add configuration-setting instructions for T-Head VECTOR vendor exten...	Jin Ma	1	-0/+4
2023-11-07	RISC-V: Add support for XCValu extension in CV32E40P	Mary Bennett	1	-0/+35
2023-11-07	RISC-V: Add support for XCVmac extension in CV32E40P	Mary Bennett	1	-0/+26
2023-11-03	RISC-V: reduce redundancy in load/store macro insn handling	Jan Beulich	1	-19/+19
2023-09-07	RISC-V: Clarify the naming rules of vendor operands.	Nelson Chu	1	-65/+65
2023-09-05	RISC-V: fold duplicate code in vector_macro()	Jan Beulich	1	-2/+2
2023-09-01	RISC-V: move various alias entries	Jan Beulich	1	-35/+35
2023-08-30	RISC-V: Make XVentanaCondOps RV64 only	Tsukasa OI	1	-2/+2
2023-08-15	RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa'	Tsukasa OI	1	-1/+1
2023-08-15	RISC-V: Add support for the 'Zihintntl' extension	Tsukasa OI	1	-0/+12
2023-08-15	RISC-V: remove indirection from register tables	Jan Beulich	1	-6/+6
2023-08-11	RISC-V: Fix opcode entries of "vmsge{,u}.vx"	Tsukasa OI	1	-4/+4
2023-08-07	RISC-V: move comment describing rules for riscv_opcodes[]	Jan Beulich	1	-10/+10
2023-08-02	Revert "2.41 Release sources"	Sam James	1	-0/+28
2023-08-02	2.41 Release sourcesbinutils-2_41-release	Nick Clifton	1	-28/+0
2023-07-18	RISC-V: Supports Zcb extension.	Jiawei	1	-0/+28
2023-07-01	RISC-V: Add support for the Zvksh ISA extension	Christoph Müllner	1	-0/+4
2023-07-01	RISC-V: Add support for the Zvksed ISA extension	Christoph Müllner	1	-0/+5