Age | Commit message (Expand) | Author | Files | Lines |
2022-01-02 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
2021-12-24 | RISC-V: Hypervisor ext: support Privileged Spec 1.12 | Vineet Gupta | 1 | -0/+21 |
2021-12-16 | RISC-V: Support svinval extension with frozen version 1.0. | Nelson Chu | 1 | -0/+7 |
2021-11-30 | RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved. | Nelson Chu | 1 | -2/+2 |
2021-11-18 | RISC-V: Add instructions and operand set for z[fdq]inx | jiawei | 1 | -148/+148 |
2021-11-17 | RISC-V: Support rvv extension with released version 1.0. | Nelson Chu | 1 | -0/+826 |
2021-11-16 | RISC-V: Scalar crypto instructions and operand set. | jiawei | 1 | -20/+72 |
2021-10-07 | RISC-V: Support aliases for Zbs instructions | Philipp Tomsich | 1 | -0/+4 |
2021-10-07 | RISC-V: Add support for Zbs instructions | Philipp Tomsich | 1 | -0/+9 |
2021-10-07 | RISC-V: Split Zb[abc] into commented sections | Philipp Tomsich | 1 | -0/+6 |
2021-04-16 | RISC-V: compress "addi d,CV,z" to "c.mv d,CV" | Lifang Xia | 1 | -0/+1 |
2021-03-16 | RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions | Kuan-Lin Chen | 1 | -4/+49 |
2021-02-19 | RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn. | Nelson Chu | 1 | -12/+22 |
2021-02-18 | RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling. | Nelson Chu | 1 | -87/+0 |
2021-02-04 | RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions. | Nelson Chu | 1 | -53/+4 |
2021-01-15 | RISC-V: Indent and GNU coding standards tidy, also aligned the code. | Nelson Chu | 1 | -710/+707 |
2021-01-15 | RISC-V: Comments tidy and improvement. | Nelson Chu | 1 | -17/+16 |
2021-01-07 | RISC-V: Add pause hint instruction. | Philipp Tomsich | 1 | -0/+3 |
2021-01-07 | RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93). | Claire Xenia Wolf | 1 | -4/+53 |
2021-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
2020-12-10 | RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions. | Nelson Chu | 1 | -0/+5 |
2020-12-10 | RISC-V: Control fence.i and csr instructions by zifencei and zicsr. | Nelson Chu | 1 | -20/+20 |
2020-12-01 | RISC-V: Remove the unimplemented extensions. | Nelson Chu | 1 | -11/+0 |
2020-12-01 | RISC-V: Add zifencei and prefixed h class extensions. | Nelson Chu | 1 | -0/+3 |
2020-06-22 | RISC-V: Report warning when linking the objects with different priv specs. | Nelson Chu | 1 | -50/+0 |
2020-06-12 | RISC-V: Drop the privileged spec v1.9 support. | Nelson Chu | 1 | -1/+0 |
2020-06-03 | RISC-V: Fix the error when building RISC-V linux native gdbserver. | Nelson Chu | 1 | -8/+8 |
2020-05-20 | [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions... | Nelson Chu | 1 | -0/+144 |
2020-02-19 | RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero. | Jim Wilson | 1 | -0/+2 |
2020-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
2019-11-12 | RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive. | Jim Wilson | 1 | -60/+60 |
2019-09-17 | RISC-V: Gate opcode tables by enum rather than string. | Jim Wilson | 1 | -658/+658 |
2019-07-30 | RISC-V: Fix minor issues with FP csr instructions. | Jim Wilson | 1 | -16/+16 |
2019-07-05 | Kito's 5-part patch set to improve .insn support. | Jim Wilson | 1 | -4/+26 |
2019-02-08 | RISC-V: Compress 3-operand beq/bne against x0. | Jim Wilson | 1 | -0/+2 |
2019-01-01 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
2018-12-07 | RISC-V: Fix 4-arg add parsing. | Jim Wilson | 1 | -1/+1 |
2018-11-29 | RISC-V: Add missing c.unimp instruction. | Jim Wilson | 1 | -1/+2 |
2018-11-27 | RISC-V: Add .insn CA support. | Jim Wilson | 1 | -2/+7 |
2018-10-02 | RISC-V: Add fence.tso instruction | Palmer Dabbelt | 1 | -0/+1 |
2018-09-17 | RISC-V: bge[u] should get higher priority than ble[u]. | Jim Wilson | 1 | -2/+2 |
2018-08-31 | RISC-V: Correct the requirement of compressed floating point instructions | Jim Wilson | 1 | -16/+16 |
2018-08-30 | RISC-V: Allow instruction require more than one extension | Jim Wilson | 1 | -629/+629 |
2018-07-30 | RISC-V: Set insn info fields correctly when disassembling. | Jim Wilson | 1 | -178/+178 |
2018-06-20 | RISC-V: Accept constant operands in la and lla | Sebastian Huber | 1 | -2/+2 |
2018-05-08 | RISC-V: Add missing hint instructions from RV128I. | Jim Wilson | 1 | -9/+45 |
2018-03-14 | RISC-V: Add .insn support. | Jim Wilson | 1 | -0/+74 |
2018-01-17 | RISC-V: Fix bug in prior addi/c.nop patch. | Jim Wilson | 1 | -1/+1 |
2018-01-15 | RISC-V: Add support for addi that compresses to c.nop. | Jim Wilson | 1 | -0/+8 |
2018-01-03 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |