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Adds two new external authors to etc/update-copyright.py to cover
bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then
updates copyright messages as follows:
1) Update cgen/utils.scm emitted copyrights.
2) Run "etc/update-copyright.py --this-year" with an extra external
author I haven't committed, 'Kalray SA.', to cover gas testsuite
files (which should have their copyright message removed).
3) Build with --enable-maintainer-mode --enable-cgen-maint=yes.
4) Check out */po/*.pot which we don't update frequently.
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There is currently a bug in the bit masking for the barrel shift
instructions because the bit mask is not including all of the
register bits which must be zero. With this patch, the disassembler
can be sure that the 32-bit value is indeed a barrel shift instruction
and not a data value in memory.
This fix can be verified by assembling and disassembling the following:
.text
.long 0x65005f5f
With this patch, the bug is fixed, and the objdump will know that
0x65005f5f is not a barrel shift instruction.
Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michael J. Eager <eager@eagercon.com>
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This patches adds new bsefi and bsifi instructions.
BSEFI- The instruction shall extract a bit field from a
register and place it right-adjusted in the destination register.
The other bits in the destination register shall be set to zero.
BSIFI- The instruction shall insert a right-adjusted bit field
from a register at another position in the destination register.
The rest of the bits in the destination register shall be unchanged.
Further documentation of these instructions can be found here:
https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref
With version 6 of the patch, no new relocation types are added as
this was unnecessary for adding the bsefi and bsifi instructions.
FIXED: Segfault caused by incorrect termination of microblaze_opcodes.
Signed-off-by: nagaraju <nagaraju.mekala@amd.com>
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michael J. Eager <eager@eagercon.com>
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This reverts commit 6bbf249557ba17cfebe01c67370df4da9e6a56f9.
Maciej W. Rozycki <macro@orcam.me.uk>:
Yet it has caused numerous regressions:
microblaze-elf +FAIL: unordered .debug_info references to .debug_ranges
microblaze-elf +FAIL: binutils-all/pr26548
microblaze-elf +FAIL: readelf -Wwi pr26548e (reason: unexpected output)
microblaze-elf +FAIL: readelf --debug-dump=loc locview-1 (reason: unexpected output) Yet it has caused numerous regressions:
microblaze-elf +FAIL: unordered .debug_info references to .debug_ranges
microblaze-elf +FAIL: binutils-all/pr26548
microblaze-elf +FAIL: readelf -Wwi pr26548e (reason: unexpected output)
...
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This patches adds new bsefi and bsifi instructions.
BSEFI- The instruction shall extract a bit field from a
register and place it right-adjusted in the destination register.
The other bits in the destination register shall be set to zero.
BSIFI- The instruction shall insert a right-adjusted bit field
from a register at another position in the destination register.
The rest of the bits in the destination register shall be unchanged.
Further documentation of these instructions can be found here:
https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref
This patch has been tested for years of AMD Xilinx Yocto
releases as part of the following patch set:
https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils
Signed-off-by: nagaraju <nagaraju.mekala@amd.com>
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michael J. Eager <eager@eagercon.com>
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The newer update-copyright.py fixes file encoding too, removing cr/lf
on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and
embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
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The result of running etc/update-copyright.py --this-year, fixing all
the files whose mode is changed by the script, plus a build with
--enable-maintainer-mode --enable-cgen-maint=yes, then checking
out */po/*.pot which we don't update frequently.
The copy of cgen was with commit d1dd5fcc38ead reverted as that commit
breaks building of bfp opcodes files.
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This is exporting the variable "opcodes" as a large writable blob.
This is not a namespace friendly name, so add a "microblaze" prefix,
and then sprinkle const over its definition & use.
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cpu/
* frv.opc: Replace bfd_boolean with bool, FALSE with false, and
TRUE with true throughout.
opcodes/
* sysdep.h (POISON_BFD_BOOLEAN): Define.
* aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
* aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
* aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
* arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
* cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
* disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
* i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
* microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
* mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
* msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
* ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
* tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
* xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
and TRUE with true throughout.
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* microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
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PR 25249
* microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
(struct string_buf): New.
(strbuf): New function.
(get_field): Use strbuf rather than strdup of local temp.
(get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
(get_field_rfsl, get_field_imm15): Likewise.
(get_field_rd, get_field_r1, get_field_r2): Update macros.
(get_field_special): Likewise. Don't strcpy spr. Formatting.
(print_insn_microblaze): Formatting. Init and pass string_buf to
get_field functions.
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With the changes done in previous patches, print_insn_XXX functions
don't have to be external visible out of opcodes, because both gdb
and objdump select disassemblers through a single interface.
This patch moves these print_insn_XXX declarations from
include/dis-asm.h to opcodes/disassemble.h, which is a new header
added by this patch.
include:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* dis-asm.h: Move some function declarations to
opcodes/disassemble.h.
opcodes:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* alpha-dis.c: Include disassemble.h, don't include
dis-asm.h.
* avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
* crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
* disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
* fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
* hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
* i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
* iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
* m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
* m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
* metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
* moxie-dis.c, msp430-dis.c, mt-dis.c:
* nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
* or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
* ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
* rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
* sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
* tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
* tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
* v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
* w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
* xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
* z80-dis.c, z8k-dis.c: Likewise.
* disassemble.h: New file.
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* microblaze-opc.h: Rename INST_TYPE_RD_R1_SPECIAL to
INST_TYPE_R1_R2_SPECIAL
* microblaze-dis.c (print_insn_microblaze): Same.
gas/Changelog
* gas/config/tc-microblaze.c: Rename INST_TYPE_RD_R1_SPECIAL to
INST_TYPE_R1_R2_SPECIAL, don't set RD for wic.
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hardware assisted stack protection, stores stack low / stack high limits
for detecting stack overflow / underflow
binutils/opcodes
* microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR
* microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK
binutils/gas
* config/tc-microblaze.c (parse_reg): Parse REG_SLR, REG_SHR
binutils/gas
* gas/microblaze/allinsn.s: Test use of SHR, SLR
* gas/microblaze/allinsn.d: Likewise
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* microblaze-opc.h: Define new instruction type INST_TYPE_IMM5,
update OPCODE_MASK_H13S, add OPCODE_MASK_HN, define MIN_IMM5 / MAX_IMM5,
and increase MAX_OPCODES.
(op_code_struct): add mbar and sleep
* microblaze-opcm.h (microblaze_instr): add mbar
Define IMM_MBAR and IMM5_MBAR_MASK
* microblaze-dis.c: Add get_field_imm5_mbar
(print_insn_microblaze): Add support for INST_TYPE_IMM5 and INST_TYPE_NONE
gas/
* config/tc-microblaze.c (md_assemble): Add support for INST_TYPE_IMM5
gas/testsuite/
* gas/microblaze/allinsn.s: Add mbar and sleep
* gas/microblaze/allinsn.d: Likewise
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* arm-dis.c: Add necessary casts for printing integer values.
Use %s when printing string values.
* hppa-dis.c: Likewise.
* m68k-dis.c: Likewise.
* microblaze-dis.c: Likewise.
* mips-dis.c: Likewise.
* ppc-dis.c: Likewise.
* sparc-dis.c: Likewise.
* dis-asm.h (fprintf_ftype): Add ATTRIBUTE_FPTR_PRINTF_2.
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Fix up all warnings generated by the addition of this switch.
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eliminate local extern decls.
* opcodes/microblaze-dis.h: New.
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* microblaze-dis.c (get_insn_microblaze, microblaze_get_target_address,
microblaze_decode_insn): Add declarations.
(get_delay_slots_microblaze): Remove.
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* bfd/Makefile.am: Add cpu-microblaze.{lo,c}, elf32-microblaze.{lo,c}.
* bfd/Makefile.in: Same.
* bfd/archures.c: Add bfd_arch_microblaze.
* bfd/bfd-in2.h: Regenerate.
* bfd/config.bfd: Add microblaze target.
* bfd/configure: Add bfd_elf32_microblaze_vec target.
* bfd/configure.in: Same.
* bfd/cpu-microblaze.c: New.
* bfd/elf32-microblaze.c: New.
* bfd/libbfd-in.h: Add prototype _bfd_dwarf2_fixup_section_debug_loc().
* bfd/libbfd.h: Regenerate.
* bfd/reloc.c: Add MICROBLAZE relocations.
* bfd/section.c: Add struct relax_table and relax_count to section.
* bfd/targets.c: Add bfd_elf32_microblaze_vec.
* binutils/MAINTAINERS: Add self as maintainer.
* binutils/readelf.c: Include elf/microblaze.h, add EM_MICROBLAZE &
EM_MICROBLAZE_OLD to guess_is_rela(), dump_relocations(),
get_machine_name().
* config.sub: Add microblaze target.
* configure: Same.
* configure.ac: Same.
* gas/Makefile.am: add microblaze to CPU_TYPES, config/tc-microblaze.c to
TARGET_CPU_CFILES, config/tc-microblaze.h to TARGET_CPU_HFILES, add
DEP_microblaze_elf target.
* gas/Makefile.in: Same.
* gas/config/tc-microblaze.c: Add MicroBlaze assembler.
* gas/config/tc-microblaze.h: Add header for tc-microblaze.c.
* gas/configure: Add microblaze target.
* gas/configure.in: Same.
* gas/configure.tgt: Same.
* gas/doc/Makefile.am: Add c-microblaze.texi to CPU_DOCS.
* gas/doc/Makefile.in: Same.
* gas/doc/all.texi: Set MICROBLAZE.
* gas/doc/as.texinfo: Add MicroBlaze doc links.
* gas/doc/c-microblaze.texi: New MicroBlaze docs.
* include/dis-asm.h: Decl print_insn_microblaze().
* include/elf/common.h: Define EM_MICROBLAZE & EM_MICROBLAZE_OLD.
* include/elf/microblaze.h: New reloc definitions.
* ld/Makefile.am: Add eelf32mb_linux.o, eelf32microblaze.o to
ALL_EMULATIONS, targets.
* ld/Makefile.in: Same.
* ld/configure.tgt: Add microblaze*-linux*, microblaze* targets.
* ld/emulparams/elf32mb_linux.sh: New.
* ld/emulparams/elf32microblaze.sh. New.
* ld/scripttempl/elfmicroblaze.sc: New.
* opcodes/Makefile.am: Add microblaze-opc.h to HFILES, microblaze-dis.c to
CFILES, microblaze-dis.lo to ALL_MACHINES, targets.
* opcodes/Makefile.in: Same.
* opcodes/configure: Add bfd_microblaze_arch target.
* opcodes/configure.in: Same.
* opcodes/disassemble.c: Define ARCH_microblaze, return
print_insn_microblaze().
* opcodes/microblaze-dis.c: New MicroBlaze disassembler.
* opcodes/microblaze-opc.h: New MicroBlaze opcode definitions.
* opcodes/microblaze-opcm.h: New MicroBlaze opcode types.
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