| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-01-17 | Replace CET bit with IBT and SHSTK bits. | Igor Tsimbalist | 1 | -15/+15 |
| 2018-01-11 | Remove VL variants for 4FMAPS and 4VNNIW insns. | Igor Tsimbalist | 1 | -12/+0 |
| 2018-01-10 | x86: fix Disp8 handling for scalar AVX512_4FMAPS insns | Jan Beulich | 1 | -2/+2 |
| 2018-01-10 | x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variants | Jan Beulich | 1 | -48/+48 |
| 2018-01-08 | x86: Properly encode vmovd with 64-bit memeory | H.J. Lu | 1 | -4/+2 |
| 2018-01-03 | Update year range in copyright notice of binutils files | Alan Modra | 1 | -1/+1 |
| 2017-12-18 | x86: fold certain AVX and AVX2 templates | Jan Beulich | 1 | -328/+164 |
| 2017-12-18 | x86: fold RegXMM/RegYMM/RegZMM into RegSIMD | Jan Beulich | 1 | -7/+7 |
| 2017-12-18 | x86: replace Reg8, Reg16, Reg32, and Reg64 | Jan Beulich | 1 | -21/+42 |
| 2017-12-15 | x86: drop stray CheckRegSize uses | Jan Beulich | 1 | -81/+81 |
| 2017-11-30 | x86: derive DispN from BaseIndex | Jan Beulich | 1 | -4113/+4113 |
| 2017-11-30 | x86: drop Vec_Disp8 | Jan Beulich | 1 | -2034/+2034 |
| 2017-11-23 | Add Disp8MemShift for AVX512 VAES instructions. | Igor Tsimbalist | 1 | -12/+12 |
| 2017-11-23 | x86: correct UDn | Jan Beulich | 1 | -2/+4 |
| 2017-11-22 | Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor. | Igor Tsimbalist | 1 | -2/+2 |
| 2017-11-22 | Remove Vec_Disp8 from vpcompressb and vpexpandb. | Igor Tsimbalist | 1 | -7/+6 |
| 2017-11-14 | x86: add support for AVX-512 VPCMP*{B,W} pseudo-ops | Jan Beulich | 1 | -19/+91 |
| 2017-11-14 | x86: string insns don't allow displacements | Jan Beulich | 1 | -19/+19 |
| 2017-11-13 | x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should not allow q suffix | Jan Beulich | 1 | -5/+5 |
| 2017-10-23 | Enable Intel AVX512_BITALG instructions. | Igor Tsimbalist | 1 | -0/+20 |
| 2017-10-23 | Enable Intel AVX512_VNNI instructions. | Igor Tsimbalist | 1 | -0/+20 |
| 2017-10-23 | Enable Intel VPCLMULQDQ instruction. | Igor Tsimbalist | 1 | -0/+14 |
| 2017-10-23 | Enable Intel VAES instructions. | Igor Tsimbalist | 1 | -0/+24 |
| 2017-10-23 | Enable Intel GFNI instructions. | Igor Tsimbalist | 1 | -0/+36 |
| 2017-10-23 | Enable Intel AVX512_VBMI2 instructions. | Igor Tsimbalist | 1 | -0/+75 |
| 2017-06-21 | x86: CET v2.0: Update incssp and setssbsy | H.J. Lu | 1 | -3/+3 |
| 2017-06-21 | x86: CET v2.0: Rename savessp to saveprevssp | H.J. Lu | 1 | -1/+1 |
| 2017-05-22 | x86: Add NOTRACK prefix support | H.J. Lu | 1 | -6/+9 |
| 2017-03-09 | X86: Add pseudo prefixes to control encoding | H.J. Lu | 1 | -68/+78 |
| 2017-03-09 | Use CpuCET on rdsspq | H.J. Lu | 1 | -1/+1 |
| 2017-03-06 | Add support for Intel CET instructions | H.J. Lu | 1 | -0/+19 |
| 2017-02-28 | x86: fix handling of 64-bit operand size VPCMPESTR{I,M} | Jan Beulich | 1 | -6/+12 |
| 2017-01-12 | Enable Intel AVX512_VPOPCNTDQ instructions | Igor Tsimbalist | 1 | -1/+9 |
| 2017-01-02 | Update year range in copyright notice of all files. | Alan Modra | 1 | -1/+1 |
| 2016-11-09 | X86: Remove the .s suffix from EVEX vpextrw | H.J. Lu | 1 | -1/+1 |
| 2016-11-09 | X86: Merge AVX512F vmovq | H.J. Lu | 1 | -8/+4 |
| 2016-11-02 | Enable Intel AVX512_4VNNIW instructions | Igor Tsimbalist | 1 | -0/+12 |
| 2016-11-02 | Enable Intel AVX512_4FMAPS instructions | Igor Tsimbalist | 1 | -0/+16 |
| 2016-10-21 | X86: Remove pcommit instruction | H.J. Lu | 1 | -6/+0 |
| 2016-08-24 | X86: Add ptwrite instruction | H.J. Lu | 1 | -0/+6 |
| 2016-07-01 | x86: allow suffix-less movzw and 64-bit movzb | Jan Beulich | 1 | -12/+3 |
| 2016-07-01 | x86: remove stray instruction attributes | Jan Beulich | 1 | -44/+44 |
| 2016-07-01 | x86/Intel: fix operand checking for MOVSD | Jan Beulich | 1 | -2/+2 |
| 2016-06-03 | Handle indirect branches for AMD64 and Intel64 | H.J. Lu | 1 | -2/+4 |
| 2016-05-27 | Replace CpuAMD64/CpuIntel64 with AMD64/Intel64 | H.J. Lu | 1 | -4/+4 |
| 2016-05-10 | Enable Intel RDPID instruction. | Alexander Fomin | 1 | -0/+7 |
| 2016-01-01 | Copyright update for binutils | Alan Modra | 1 | -1/+1 |
| 2015-12-09 | Implement Intel OSPKE instructions | H.J. Lu | 1 | -0/+7 |
| 2015-06-30 | Add support for monitorx/mwaitx instructions | Amit Pawar | 1 | -0/+13 |
| 2015-06-01 | x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s} | Jan Beulich | 1 | -0/+6 |
