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AgeCommit message (Expand)AuthorFilesLines
2024-06-10x86/APX: convert ZU to operand constraintJan Beulich1-2/+5
2024-06-10x86/APX: support extended SETcc formJan Beulich1-1/+4
2024-06-10x86/APX: add missing CPU requirement to imm+rm forms of <alu2> insnsJan Beulich1-1/+1
2024-05-29x86/Intel: warn about undue mnemonic suffixesJan Beulich1-87/+87
2024-05-24x86: correct VCVT{,U}SI2SDJan Beulich1-8/+8
2024-05-22Support APX zero-upperCui, Lili1-0/+6
2024-05-06x86: Drop using extension_opcode to encode vvvv registerCui, Lili1-59/+61
2024-05-06x86: Drop SwapSourcesCui, Lili1-30/+30
2024-05-06x86: Use vexvvvv as the switch state to encode the vvvv registerCui, Lili1-565/+566
2024-05-03x86: tidy <sse*> templatesJan Beulich1-20/+20
2024-05-03x86/APX: further extend SSE2AVX coverageJan Beulich1-5/+6
2024-05-03x86/APX: extend SSE2AVX coverageJan Beulich1-201/+303
2024-04-17Add W table for USER_MSR under MAP4.Hu, Lin11-1/+1
2024-04-07Support APX NFCui, Lili1-2/+21
2024-04-06Revert "x86: Restore APX shift-double instructions with omitted shift count"H.J. Lu1-1/+0
2024-04-04x86: Restore APX shift-double instructions with omitted shift countH.J. Lu1-0/+1
2024-04-03x86: add missing No_qSuf to non-64-bit PTWRITEJan Beulich1-1/+1
2024-04-03x86: drop stray Size64 from WRSSQJan Beulich1-2/+2
2024-04-03x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4Cui, Lili1-18/+0
2024-03-28x86: templatize RAO-INT insnsJan Beulich1-8/+4
2024-03-28x86: templatize ADX insnsJan Beulich1-6/+5
2024-03-28x86: templatize shift-double insnsJan Beulich1-13/+9
2024-03-28x86: templatize shift/rotate insnsJan Beulich1-71/+22
2024-03-28x86: templatize binary ALU insnsJan Beulich1-59/+23
2024-03-28x86: templatize unary ALU insnsJan Beulich1-10/+16
2024-03-28x86: templatize INC/DECJan Beulich1-8/+8
2024-03-01x86/APX: optimize certain XOR and SUB formsJan Beulich1-2/+2
2024-02-23x86/APX: INV{EPT,PCID,VPID} are WIGJan Beulich1-3/+3
2024-02-16x86/APX: drop stray IgnoreSizeJan Beulich1-11/+11
2024-02-16x86: don't use VexWIG in SSE2AVX templatesJan Beulich1-4/+4
2024-02-16x86: drop redundant XmmwordJan Beulich1-8/+8
2024-02-09x86/APX: V{BROADCAST,EXTRACT,INSERT}{F,I}128 can also be expressedJan Beulich1-4/+16
2024-02-09x86/APX: VROUND{P,S}{S,D} encodings require AVX512{F,VL}Jan Beulich1-2/+2
2024-01-26x86/APX: optimize MOVBEJan Beulich1-2/+4
2024-01-19x86/APX: VROUND{P,S}{S,D} can generally be encodedJan Beulich1-0/+4
2024-01-19x86: drop redundant EVex128 from PUSH2/POP2Jan Beulich1-4/+4
2024-01-19x86: support APX forms of U{RD,WR}MSRJan Beulich1-2/+4
2024-01-15opcodes: x86: new marker for insns that implicitly update stack pointerIndu Bhagat1-52/+53
2024-01-15opcodes: gas: x86: define and use Rex2 as attribute not constraintIndu Bhagat1-1/+0
2024-01-09x86: add missing APX logic to cpu_flags_match()Jan Beulich1-1/+7
2024-01-04Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2023-12-28Support APX pushp/poppCui, Lili1-0/+3
2023-12-28Support APX Push2/Pop2Mo, Zewei1-0/+9
2023-12-28Support APX NDDkonglin11-0/+75
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili1-25/+65
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili1-13/+14
2023-12-19x86: Remove the restriction for size of the mask register in AVX10Haochen Jiang1-22/+19
2023-12-15revert "x86: allow 32-bit reg to be used with U{RD,WR}MSR"Jan Beulich1-2/+2
2023-12-15x86: fold assembly dialect attributesJan Beulich1-0/+4
2023-12-15x86: Intel syntax implies Intel mnemonicsJan Beulich1-20/+16