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path: root/opcodes/i386-opc.tbl
AgeCommit message (Expand)AuthorFilesLines
2019-06-25x86: fix (dis)assembly of certain SSE2 insns in 16-bit modeJan Beulich1-1/+1
2019-06-25x86-64: also optimize ANDQ with immediate fitting in 7 bitsJan Beulich1-1/+1
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu1-0/+7
2019-06-04Add support for Intel ENQCMD[S] instructionsH.J. Lu1-0/+9
2019-05-28x86: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVLH.J. Lu1-2/+2
2019-04-08x86: Consolidate AVX512 BF16 entries in i386-opc.tblH.J. Lu1-22/+7
2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo1-0/+30
2019-03-18x86: Optimize EVEX vector load/store instructionsH.J. Lu1-6/+6
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-11-06x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich1-9/+9
2018-11-06x86: adjust {,E}VEX.W handling outside of 64-bit modeJan Beulich1-16/+16
2018-11-06x86: fix various non-LIG templatesJan Beulich1-43/+53
2018-11-06x86: allow {store} to select alternative {,}PEXTRW encodingJan Beulich1-7/+6
2018-11-06x86: add more VexWIGJan Beulich1-143/+143
2018-11-06x86: XOP VPHADD* / VPHSUB* are VEX.W0Jan Beulich1-17/+19
2018-10-10x86: fold Size{16,32,64} template attributesJan Beulich1-0/+4
2018-10-05x86: Add Intel ENCLV to assembler and disassemblerH.J. Lu1-0/+1
2018-09-17x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu1-4/+4
2018-09-17x86: Set Vex=1 on VEX.128 only vmovd and vmovqH.J. Lu1-8/+8
2018-09-17x86: Replace VexW=3 with VexWIGH.J. Lu1-468/+470
2018-09-15x86: Set VexW=3 on AVX vrsqrtssH.J. Lu1-1/+1
2018-09-15x86: Set Vex=1 on VEX.128 only vmovqH.J. Lu1-2/+2
2018-09-14x86: Support VEX/EVEX WIG encodingH.J. Lu1-467/+467
2018-09-14x86: fold CRC32 templatesJan Beulich1-6/+2
2018-09-13x86: Remove VexW=1 from WIG VEX movq and vmovqH.J. Lu1-4/+4
2018-09-13i386: Update VexW field for VEX instructionsH.J. Lu1-18/+18
2018-09-13x86: drop bogus IgnoreSize from a few further insnsJan Beulich1-26/+26
2018-09-13x86: drop bogus IgnoreSize from AVX512_4* insnsJan Beulich1-6/+6
2018-09-13x86: drop bogus IgnoreSize from AVX512DQ insnsJan Beulich1-48/+48
2018-09-13x86: drop bogus IgnoreSize from AVX512BW insnsJan Beulich1-40/+40
2018-09-13x86: drop bogus IgnoreSize from AVX512VL insnsJan Beulich1-13/+13
2018-09-13x86: drop bogus IgnoreSize from AVX512ER insnsJan Beulich1-16/+16
2018-09-13x86: drop bogus IgnoreSize from AVX512F insnsJan Beulich1-371/+371
2018-09-13x86: drop bogus IgnoreSize from SHA insnsJan Beulich1-8/+8
2018-09-13x86: drop bogus IgnoreSize from XOP and SSE4a insnsJan Beulich1-133/+133
2018-09-13x86: drop bogus IgnoreSize from AVX2 insnsJan Beulich1-119/+119
2018-09-13x86: drop bogus IgnoreSize from AVX insnsJan Beulich1-128/+128
2018-09-13x86: drop bogus IgnoreSize from GNFI insnsJan Beulich1-6/+6
2018-09-13x86: drop bogus IgnoreSize from PCLMUL/VPCLMUL insnsJan Beulich1-16/+16
2018-09-13x86: drop bogus IgnoreSize from AES/VAES insnsJan Beulich1-22/+22
2018-09-13x86: drop bogus IgnoreSize from SSE4.2 insnsJan Beulich1-10/+10
2018-09-13x86: drop bogus IgnoreSize from SSE4.1 insnsJan Beulich1-63/+63
2018-09-13x86: drop bogus IgnoreSize from SSSE3 insnsJan Beulich1-32/+32
2018-09-13x86: drop bogus IgnoreSize from SSE3 insnsJan Beulich1-18/+18
2018-09-13x86: drop bogus IgnoreSize from SSE2 insnsJan Beulich1-208/+208
2018-09-13x86: drop bogus IgnoreSize from SSE insnsJan Beulich1-59/+59
2018-09-13x86: drop unnecessary {,No}Rex64Jan Beulich1-5/+5
2018-09-13x86: also allow D on 3-operand insnsJan Beulich1-8/+4
2018-09-13x86: use D attribute also for SIMD templatesJan Beulich1-134/+62
2018-08-11x86: Add CpuCMOV and CpuFXSRH.J. Lu1-34/+34
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