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path: root/opcodes/i386-opc.tbl
AgeCommit message (Expand)AuthorFilesLines
2021-07-14x86: Add int1 as one byte opcode 0xf1H.J. Lu1-0/+1
2021-04-26x86: optimize LEAJan Beulich1-1/+1
2021-03-29x86: move some opcode table entriesJan Beulich1-30/+31
2021-03-29x86: VPSADBW's source operands are also commutativeJan Beulich1-3/+3
2021-03-29x86: fold SSE2AVX and their base MMX/SSE templatesJan Beulich1-567/+281
2021-03-29x86: undo Prefix_0X<nn> use in opcode tableJan Beulich1-369/+365
2021-03-26x86-64: don't accept supposedly disabled MOVQ formsJan Beulich1-2/+2
2021-03-25x86: fix AMD Zen3 insnsJan Beulich1-3/+7
2021-03-24x86: derive opcode length from opcode valueJan Beulich1-3409/+3409
2021-03-24x86: don't use opcode_length to identify pseudo prefixesJan Beulich1-13/+8
2021-03-23x86: split opcode prefix and opcode space representationJan Beulich1-2142/+2149
2021-03-09x86: fold some prefix related attributes into a single oneJan Beulich1-41/+48
2021-03-09x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich1-1/+1
2021-03-03x86: infer operand count of templatesJan Beulich1-3419/+3419
2021-02-16x86: CVTPI2PD has special behaviorJan Beulich1-1/+3
2021-02-16x86: have preprocessor expand macrosJan Beulich1-0/+5
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-0/+26
2020-10-16Enhancement for avx-vnni patchCui,Lili1-4/+4
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-0/+10
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-0/+6
2020-10-14x86: Support Intel UINTRLili Cui1-0/+10
2020-10-14x86: Remove the prefix byte from non-VEX/EVEX base_opcodeH.J. Lu1-344/+344
2020-10-13x86: Rename VexOpcode to OpcodePrefixH.J. Lu1-2140/+2144
2020-09-24Add support for Intel TDX instructions.Cui,Lili1-0/+9
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-0/+16
2020-07-30x86: Add {disp16} pseudo prefixH.J. Lu1-10/+11
2020-07-10x86: Add support for Intel AMX instructionsLili Cui1-0/+23
2020-07-08x86: FMA4 scalar insns ignore VEX.LJan Beulich1-16/+16
2020-07-02x86: Add SwapSourcesH.J. Lu1-5/+5
2020-06-26i386-opc.tbl: Add a blank lineH.J. Lu1-0/+1
2020-06-26x86: Correct VexSIB128 to VecSIB128H.J. Lu1-27/+27
2020-06-26x86: Rename VecSIB to SIB for Intel AMXH.J. Lu1-78/+81
2020-06-14x86: Correct xsusldtrk mnemonicH.J. Lu1-1/+1
2020-04-07Add support for intel TSXLDTRK instructions$Cui,Lili1-0/+7
2020-04-02Add support for intel SERIALIZE instructionLiliCui1-0/+6
2020-03-09x86: use template for AVX512 integer comparison insnsJan Beulich1-48/+10
2020-03-09x86: use template for XOP integer comparison, shift, and rotate insnsJan Beulich1-100/+13
2020-03-09x86: use template for AVX/AVX512 floating point comparison insnsJan Beulich1-496/+22
2020-03-09x86: use template for SSE floating point comparison insnsJan Beulich1-64/+10
2020-03-09x86: allow opcode templates to be templatedJan Beulich1-90/+6
2020-03-06x86: reduce amount of various VCVT* templatesJan Beulich1-30/+20
2020-03-06x86: drop/replace IgnoreSizeJan Beulich1-699/+699
2020-03-06x86: don't accept FI{LD,STP,STTP}LL in Intel syntax modeJan Beulich1-3/+3
2020-03-06x86: replace NoRex64 on VEX-encoded insnsJan Beulich1-25/+25
2020-03-06x86: drop Rex64 attributeJan Beulich1-18/+18
2020-03-06x86: add missing IgnoreSizeJan Beulich1-18/+18
2020-03-06x86: refine TPAUSE and UMWAITJan Beulich1-4/+4
2020-03-04x86: support VMGEXITJan Beulich1-0/+1
2020-03-03x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu1-0/+3
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