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path: root/opcodes/i386-opc.tbl
AgeCommit message (Expand)AuthorFilesLines
2020-07-30x86: Add {disp16} pseudo prefixH.J. Lu1-10/+11
2020-07-10x86: Add support for Intel AMX instructionsLili Cui1-0/+23
2020-07-08x86: FMA4 scalar insns ignore VEX.LJan Beulich1-16/+16
2020-07-02x86: Add SwapSourcesH.J. Lu1-5/+5
2020-06-26i386-opc.tbl: Add a blank lineH.J. Lu1-0/+1
2020-06-26x86: Correct VexSIB128 to VecSIB128H.J. Lu1-27/+27
2020-06-26x86: Rename VecSIB to SIB for Intel AMXH.J. Lu1-78/+81
2020-06-14x86: Correct xsusldtrk mnemonicH.J. Lu1-1/+1
2020-04-07Add support for intel TSXLDTRK instructions$Cui,Lili1-0/+7
2020-04-02Add support for intel SERIALIZE instructionLiliCui1-0/+6
2020-03-09x86: use template for AVX512 integer comparison insnsJan Beulich1-48/+10
2020-03-09x86: use template for XOP integer comparison, shift, and rotate insnsJan Beulich1-100/+13
2020-03-09x86: use template for AVX/AVX512 floating point comparison insnsJan Beulich1-496/+22
2020-03-09x86: use template for SSE floating point comparison insnsJan Beulich1-64/+10
2020-03-09x86: allow opcode templates to be templatedJan Beulich1-90/+6
2020-03-06x86: reduce amount of various VCVT* templatesJan Beulich1-30/+20
2020-03-06x86: drop/replace IgnoreSizeJan Beulich1-699/+699
2020-03-06x86: don't accept FI{LD,STP,STTP}LL in Intel syntax modeJan Beulich1-3/+3
2020-03-06x86: replace NoRex64 on VEX-encoded insnsJan Beulich1-25/+25
2020-03-06x86: drop Rex64 attributeJan Beulich1-18/+18
2020-03-06x86: add missing IgnoreSizeJan Beulich1-18/+18
2020-03-06x86: refine TPAUSE and UMWAITJan Beulich1-4/+4
2020-03-04x86: support VMGEXITJan Beulich1-0/+1
2020-03-03x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu1-0/+3
2020-03-03x86: Allow integer conversion without suffix in AT&T syntaxH.J. Lu1-10/+20
2020-02-17x86: Remove CpuABM and add CpuPOPCNTH.J. Lu1-3/+5
2020-02-17x86: fold certain VCVT{,U}SI2S{S,D} templatesJan Beulich1-21/+15
2020-02-17x86: fold AddrPrefixOpReg templatesJan Beulich1-24/+15
2020-02-17x86/Intel: improve diagnostics for ambiguous VCVT* operandsJan Beulich1-13/+23
2020-02-14Remove Intel syntax comments on movsx and movzxH.J. Lu1-3/+2
2020-02-14x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZXJan Beulich1-12/+5
2020-02-12x86: correct VFPCLASSP{S,D} operand size handlingJan Beulich1-2/+4
2020-02-12x86: fold two JMP templatesJan Beulich1-2/+1
2020-02-12x86-64: Intel64 adjustments for insns dealing with far pointersJan Beulich1-11/+16
2020-02-11x86: drop ShortForm attributeJan Beulich1-95/+95
2020-02-11x86: drop stray ShortForm attributesJan Beulich1-6/+6
2020-02-10x86: Accept Intel64 only instruction by defaultH.J. Lu1-11/+15
2020-01-30x86-64: honor vendor specifics for near RETJan Beulich1-2/+4
2020-01-30x86: drop further pointless/bogus DefaultSizeJan Beulich1-9/+9
2020-01-27x86-64: Properly encode and decode movsxdH.J. Lu1-1/+3
2020-01-21x86: improve handling of insns with ambiguous operand sizesJan Beulich1-1/+1
2020-01-21x86: VCVTNEPS2BF16{X,Y} should permit broadcastingJan Beulich1-2/+2
2020-01-17x86: Add {vex} pseudo prefixH.J. Lu1-0/+1
2020-01-16x86: drop stale Vec_Imm4 related commentJan Beulich1-2/+0
2020-01-16x86: add a few more missing VexWIGJan Beulich1-4/+4
2020-01-16x86: VPEXTRQ/VPINSRQ are unavailable outside of 64-bit modeJan Beulich1-8/+8
2020-01-09x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMDJan Beulich1-2/+4
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-12-27x86: consolidate Disp<NN> handling a littleJan Beulich1-18/+15
2019-12-04x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifierJan Beulich1-3/+3
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