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path: root/opcodes/i386-dis.c
AgeCommit message (Expand)AuthorFilesLines
2023-04-21x86: change fetch error handling in top-level functionJan Beulich1-13/+59
2023-04-21x86: move fetch error handling into a helper functionJan Beulich1-28/+35
2023-04-07Support Intel AMX-COMPLEXHaochen Jiang1-1/+33
2023-03-20Revert "segfault at i386-dis.c:9815"Alan Modra1-9/+4
2023-03-19segfault at i386-dis.c:9815Alan Modra1-4/+9
2023-01-20x86: embed register and alike names in disassemblerJan Beulich1-34/+34
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2022-12-12x86: revert disassembler parts of "x86: Allow 16-bit register source for LAR ...Jan Beulich1-2/+14
2022-12-06x86: Remove unnecessary vex.w check for xh_mode in disassemblerHaochen Jiang1-17/+12
2022-12-03x86: Allow 16-bit register source for LAR and LSLH.J. Lu1-14/+2
2022-11-24x86: correct handling of LAR and LSLJan Beulich1-2/+14
2022-11-15Add AMD znver4 processor supportTejas Joshi1-1/+15
2022-11-08x86: Correct wrong comments in vex_w_tableHaochen Jiang1-1/+1
2022-11-08Support Intel RAO-INTKong Lingling1-1/+10
2022-11-04Support Intel AVX-NE-CONVERTkonglin11-3/+43
2022-11-02Support Intel MSRLISTHu, Lin11-0/+17
2022-11-02Support Intel WRMSRNSHu, Lin11-0/+7
2022-11-02Support Intel CMPccXADDHaochen Jiang1-17/+130
2022-11-02Support Intel AVX-VNNI-INT8Cui,Lili1-3/+20
2022-11-02Support Intel AVX-IFMAHongyu Wang1-2/+14
2022-10-31Support Intel PREFETCHICui, Lili1-2/+76
2022-10-24x86: emit {evex} prefix when disassembling ambiguous AVX512VL insnsJan Beulich1-86/+122
2022-10-21Support Intel AMX-FP16Cui,Lili1-0/+18
2022-10-17x86: fold AVX512-VNNI disassembler entries with AVX-VNNI onesJan Beulich1-11/+18
2022-09-12x86: avoid i386_dis_printf()'s staging area for a fair part of outputJan Beulich1-20/+24
2022-08-16i386: Add MAX_OPERAND_BUFFER_SIZEH.J. Lu1-3/+6
2022-08-01Get rid of fprintf_vma and sprintf_vmaAlan Modra1-17/+4
2022-06-15x86: drop print_operand_value()'s "hex" parameterJan Beulich1-55/+16
2022-06-13x86: fix incorrect indirectionJan Beulich1-1/+1
2022-06-13x86: replace global scratch bufferJan Beulich1-126/+97
2022-06-13x86: avoid string copy when swapping Vex.W controlled operandsJan Beulich1-6/+8
2022-06-13x86: shrink prefix related disassembler state fieldsJan Beulich1-27/+28
2022-06-13x86: properly initialize struct instr_info instance(s)Jan Beulich1-257/+235
2022-06-08libopcodes: extend the styling within the i386 disassemblerAndrew Burgess1-137/+286
2022-05-27opcodes/i386: remove trailing whitespace from insns with zero operandsAndrew Burgess1-5/+22
2022-05-27x86/Intel: adjust representation of embedded rounding / SAEJan Beulich1-0/+17
2022-05-27x86/Intel: adjust representation of embedded broadcastJan Beulich1-4/+11
2022-05-18x86: shrink op_riprelJan Beulich1-18/+12
2022-05-07Fix multiple ubsan warnings in i386-dis.cAlan Modra1-13/+13
2022-04-19x86: correct and simplify NOP disassemblyJan Beulich1-21/+9
2022-04-04opcodes/i386: partially implement disassembler style supportAndrew Burgess1-23/+40
2022-03-24x86: drop L1OM special case from disassemblerJan Beulich1-6/+2
2022-02-15x86: Add has_sib to struct instr_infoH.J. Lu1-8/+9
2022-01-17x86: adjust struct instr_info field typesJan Beulich1-36/+39
2022-01-17x86: drop index16 fieldJan Beulich1-5/+3
2022-01-17x86: drop most Intel syntax register name arraysJan Beulich1-230/+119
2022-01-17x86: fold variables in memory operand index handlingJan Beulich1-19/+15
2022-01-17x86: constify disassembler static dataJan Beulich1-58/+58
2022-01-14x86: drop ymmxmm_modeJan Beulich1-16/+0
2022-01-14x86: share yet more VEX table entries with EVEX decodingJan Beulich1-73/+53
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