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authorH.J. Lu <hjl.tools@gmail.com>2022-12-02 18:43:20 -0800
committerH.J. Lu <hjl.tools@gmail.com>2022-12-03 08:55:40 -0800
commit859aa2c86dc9721424d96584879385a18ccf76ed (patch)
treeac18e5d21dbd85c8ddf575ed9b698a2c3fbc6cb5 /opcodes/i386-dis.c
parent8169d2a118c45f8a79cb3e00039ec1d01e994d9c (diff)
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x86: Allow 16-bit register source for LAR and LSL
Since LAR and LSL only access 16 bits of the source operand, regardless of operand size, allow 16-bit register source for LAR and LSL, and always disassemble LAR and LSL with 16-bit source operand. gas/ PR gas/29844 * testsuite/gas/i386/i386.s: Add tests for LAR and LSL. * testsuite/gas/i386/x86_64.s: Likewise. * testsuite/gas/i386/intelbad.s: Remove "lar/lsl eax, ax". * testsuite/gas/i386/i386-intel.d: Updated. * testsuite/gas/i386/i386.d: Likewise. * testsuite/gas/i386/intel-intel.d: Likewise. * testsuite/gas/i386/intel.d: Likewise. * testsuite/gas/i386/intelbad.l: Likewise. * testsuite/gas/i386/x86_64-intel.d: Likewise. * testsuite/gas/i386/x86_64.d: Likewise. opcodes/ PR gas/29844 * i386-dis.c (MOD_0F02): Removed. (MOD_0F03): Likewise. (dis386_twobyte): Restore larS and lslS. (mod_table): Remove MOD_0F02 and MOD_0F03. * i386-opc.tbl: Allow 16-bit register source for LAR and LSL. * i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes/i386-dis.c')
-rw-r--r--opcodes/i386-dis.c16
1 files changed, 2 insertions, 14 deletions
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index edc2ce9..e43666a 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -833,8 +833,6 @@ enum
MOD_0F01_REG_3,
MOD_0F01_REG_5,
MOD_0F01_REG_7,
- MOD_0F02,
- MOD_0F03,
MOD_0F12_PREFIX_0,
MOD_0F12_PREFIX_2,
MOD_0F13,
@@ -2117,8 +2115,8 @@ static const struct dis386 dis386_twobyte[] = {
/* 00 */
{ REG_TABLE (REG_0F00 ) },
{ REG_TABLE (REG_0F01 ) },
- { MOD_TABLE (MOD_0F02) },
- { MOD_TABLE (MOD_0F03) },
+ { "larS", { Gv, Ew }, 0 },
+ { "lslS", { Gv, Ew }, 0 },
{ Bad_Opcode },
{ "syscall", { XX }, 0 },
{ "clts", { XX }, 0 },
@@ -8200,16 +8198,6 @@ static const struct dis386 mod_table[][2] = {
{ RM_TABLE (RM_0F01_REG_7_MOD_3) },
},
{
- /* MOD_0F02 */
- { "larS", { Gv, Mw }, 0 },
- { "larS", { Gv, Ev }, 0 },
- },
- {
- /* MOD_0F03 */
- { "lslS", { Gv, Mw }, 0 },
- { "lslS", { Gv, Ev }, 0 },
- },
- {
/* MOD_0F12_PREFIX_0 */
{ "movlpX", { XM, EXq }, 0 },
{ "movhlps", { XM, EXq }, 0 },