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| author | Jan Beulich <jbeulich@suse.com> | 2022-11-24 09:34:52 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2022-11-24 09:34:52 +0100 |
| commit | c9f5b96bdab031e9520d98e01ee1bef1ffd3b961 (patch) | |
| tree | 7bf77e81e28c7d8fda786174240f22c2166d057c /opcodes/i386-dis.c | |
| parent | bde9f9d7e978b190ff6fc7207e2fe293d7c989a7 (diff) | |
| download | gdb-c9f5b96bdab031e9520d98e01ee1bef1ffd3b961.zip gdb-c9f5b96bdab031e9520d98e01ee1bef1ffd3b961.tar.gz gdb-c9f5b96bdab031e9520d98e01ee1bef1ffd3b961.tar.bz2 | |
x86: correct handling of LAR and LSL
Both uniformly only ever take 16-bit memory operands while at the same
time requiring matching (in size) register operands, which then also
should disassemble that way. This in particular requires splitting each
of the templates for the assembler and separating decode of the
register and memory forms in the disassembler.
Diffstat (limited to 'opcodes/i386-dis.c')
| -rw-r--r-- | opcodes/i386-dis.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index e43666a..edc2ce9 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -833,6 +833,8 @@ enum MOD_0F01_REG_3, MOD_0F01_REG_5, MOD_0F01_REG_7, + MOD_0F02, + MOD_0F03, MOD_0F12_PREFIX_0, MOD_0F12_PREFIX_2, MOD_0F13, @@ -2115,8 +2117,8 @@ static const struct dis386 dis386_twobyte[] = { /* 00 */ { REG_TABLE (REG_0F00 ) }, { REG_TABLE (REG_0F01 ) }, - { "larS", { Gv, Ew }, 0 }, - { "lslS", { Gv, Ew }, 0 }, + { MOD_TABLE (MOD_0F02) }, + { MOD_TABLE (MOD_0F03) }, { Bad_Opcode }, { "syscall", { XX }, 0 }, { "clts", { XX }, 0 }, @@ -8198,6 +8200,16 @@ static const struct dis386 mod_table[][2] = { { RM_TABLE (RM_0F01_REG_7_MOD_3) }, }, { + /* MOD_0F02 */ + { "larS", { Gv, Mw }, 0 }, + { "larS", { Gv, Ev }, 0 }, + }, + { + /* MOD_0F03 */ + { "lslS", { Gv, Mw }, 0 }, + { "lslS", { Gv, Ev }, 0 }, + }, + { /* MOD_0F12_PREFIX_0 */ { "movlpX", { XM, EXq }, 0 }, { "movhlps", { XM, EXq }, 0 }, |