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8 daysx86: Correct position of ".s" for CCMPcc in disassemblerCui, Lili1-2/+2
Added new macro %SW to CCMPcc to print ".s" after the mnemonic. Before: ccmpbl {dfv=}.s %edx,%eax After: ccmpbl.s {dfv=} %edx,%eax gas/ChangeLog: * testsuite/gas/i386/x86-64-pseudos-apx.d: Add tests for CCMPcc. * testsuite/gas/i386/x86-64-pseudos-apx.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Added %SW for CCMPcc swap operands. * i386-dis.c (struct dis386): Added %SW. (putop): Handle %SW.
2024-06-18Remove %ME and used %NE for movbe.Cui, Lili1-2/+2
%ME is added specifically for movbe. Now with %NE, we can use MOD table + %NE to indicate whether a {evex} prefix is needed. opcodes/ChangeLog: * i386-dis-evex-mod.h: Added movbe. * i386-dis-evex.h: Let movbe go through the mod table. * i386-dis.c (struct dis386): Removed %ME. (putop): Removed case ME.
2024-06-18Support APX CCMP and CTESTCui, Lili1-6/+6
CCMP and CTEST are two new sets of instructions for conditional CMP and TEST, SCC and OSZC flags are given as suffixes of CCMP or CTEST in the instruction mnemonic, e.g.: ccmp<cc> { dfv=sf , cf , of } %eax, %ecx also add {evex} cmp/test %eax, %ecx as an alias for ccmpt. For the encoder part, add function check_Scc_OszcOperation to parse '{ dfv=of , sf, sf, cf}', store scc in the lower 4 bits of base_opcode, and adjust base_opcode to its normal meaning in install_template. For the decoder part, add 'SC' and 'DF' macros to add scc and oszc flags suffixes. gas/ChangeLog: * config/tc-i386.c (OSZC_CF): New. (OSZC_ZF): Ditto. (OSZC_SF): Ditto. (OSZC_OF): Ditto. (set_oszc_flags): Set oszc flags and report error for using the same oszc flags twice. (check_Scc_OszcOperations): Handle SCC OSZC flags. (install_template): Add scc and oszc_flags. (build_apx_evex_prefix): Encode SCC and oszc flags bits. (parse_insn): Handle check_Scc_OszcOperations. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add ivalid test case. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add test for ccmp and ctest. * testsuite/gas/i386/x86-64-apx-ccmp-ctest-intel.d: New test. * testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-ccmp-ctest-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-ccmp-ctest.d: Ditto. * testsuite/gas/i386/x86-64-apx-ccmp-ctest.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-reg.h: Add ccmp and ctest. * i386-dis-evex.h: Ditto. * i386-dis.c (struct instr_info): add scc. (struct dis386): Add new micro 'NE','SC' and'DF'. (get_valid_dis386): Get scc value and move MAP4 invalid check to print_insn. (putop): Handle %NE, %SC and %DF. * i386-opc.h (SCC): New. * i386-opc.tbl: Add ccmp/ctest and evex format for cmp/test. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto.
2024-06-10x86: disassembler macro for condition codeJan Beulich1-32/+32
Both CMPccXADD and APX'es {,CF}CMOVcc have almost identical entries replicated 16 times each. Fold those to just one each by introducing a %CC macro. (Note that the recording of ->condition_code in print_insn() is merely for completeness for now; it's not used as long as only VEX/EVEX encodings would consume it.) This then also renders condition codes printed consistent across all respective insns; CMPxxXADD had a number of outliers so far.
2024-05-22Support APX zero-upperCui, Lili1-18/+18
This patch is to enable ZU for IMUL (opcodes 0x69 and 0x6B) and SETcc. Since the spec only recommends one form of setzu, I won't be adding set<cc>reg32/reg64 support in this patch. gas/ChangeLog: * config/tc-i386.c (build_apx_evex_prefix): Handle ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64.exp: Added new tests for ZU. * testsuite/gas/i386/x86-64-apx-zu-intel.d: New test. * testsuite/gas/i386/x86-64-apx-zu-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-zu-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-zu.d: Ditto. * testsuite/gas/i386/x86-64-apx-zu.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_MAP4_40 ~ PREFIX_EVEX_MAP4_4F. * i386-dis-evex.h: Ditto. * i386-dis.c (struct dis386): Add new micro 'ZU'. (putop): Handle %ZU. * i386-gen.c: Added ZU. * i386-opc.h: Ditto. * i386-opc.tbl: Added new templates to support ZU.
2024-04-09Support {evex} pseudo prefix for decode evex promoted insns without egpr32.Hu, Lin11-2/+2
This patch is based on APX NF patch and also adds test cases for Checking 64-bit insns not sizeable through register operands with evex. gas/ChangeLog: * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Added no-egpr testcases for movbe. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto. * testsuite/gas/i386/x86-64.exp: Added tests. * testsuite/gas/i386/noreg64-evex.d: New test. * testsuite/gas/i386/noreg64-evex.e: Ditto. * testsuite/gas/i386/noreg64-evex.s: Ditto. * testsuite/gas/i386/x86-64-apx_f-evex.d: Ditto. * testsuite/gas/i386/x86-64-apx_f-evex.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Added %ME to movbe. * i386-dis.c : Added %XE to evex_from_vex instructions to output {evex}. (struct dis386): New %ME. (putop): Handle %ME and output {evex} for evex_from_legacy instructions. * Return early when the instruction name is (bad).
2024-04-07Support APX NFCui, Lili1-38/+38
For the case when NDD and NF are both 0 in evex-promoted format, we will fully support and test it in another patch. gas/ChangeLog: * NEWS: Support Intel APX NF. * config/tc-i386.c (enum i386_error): Add unsupported_nf. (struct _i386_insn): Add has_nf. (is_apx_evex_encoding): Ditto. (build_apx_evex_prefix): Encode the NF bit. (md_assemble): Handle unsupported_nf. (parse_insn): Handle Prefix_NF and report bad for illegal combination. (can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf. (match_template): Support D for APX_F insns and check NF support. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-inval.s: Ditto. * testsuite/gas/i386/x86-64.exp: Add apx nf tests. * testsuite/gas/i386/x86-64-apx-nf-intel.d: New test. * testsuite/gas/i386/x86-64-apx-nf.d: Ditto. * testsuite/gas/i386/x86-64-apx-nf.s: Ditto. opcodes/ChangeLog: * i386-dis-evex.h: Add %NF to the instructions that support APX NF and add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table. * i386-dis-evex-reg.h: Ditto. * i386-dis.c (struct instr_info): Add nf. (struct dis386): Add "NF" for EVEX.NF. (get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case. (print_insn): Handle ins.vex.nf. (putop): Handle "%NF". * i386-opc.h (Prefix_NF): New. * i386-opc.tbl: Added new entries to support full APX NF instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Regenerated.
2024-04-03x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4Cui, Lili1-9/+9
APX spec removed KEYLOCKER and SHA promotions from EVEX MAP4. https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html gas/ChangeLog: * NEWS: Mention that remove KEYLOCKER and SHA promotions from EVEX * MAP4. * config/tc-i386.c (process_operands): Removed special handling of * KEYLOCKER and SHA. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: Removed KEYLOCKER * and SHA instructions. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Removed KEYLOCKER and SHA instructions. * i386-dis-evex.h: Ditto. * i386-opc.tbl: Ditto. * i386-dis.c (print_vector_reg): Removed special handling of KEYLOCKER * and SHA.
2024-01-26x86/APX: TILE{RELEASE,ZERO} have no EVEX encodingsJan Beulich1-2/+2
Re-using the entire VEX decode hierarchy for the respective major opcode has led to those two also being decoded as-if valid. Follow the earlier USE_X86_64_EVEX_{PFX,W}_TABLE approach to avoid this happening.
2024-01-26x86/APX: no need to have decode go through x86_64_table[]Jan Beulich1-10/+10
As suggested during review already, all such entries have their first slot as Bad_Opcode, so by adding two more enumerators we can avoid doing that decode step altogether.
2023-12-28Support APX Push2/Pop2Mo, Zewei1-1/+1
PPX functionality for PUSH/POP is not implemented in this patch and will be implemented separately. gas/ChangeLog: 2023-12-28 Zewei Mo <zewei.mo@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c: (enum i386_error): New unsupported_rsp_register and invalid_src_register_set. (md_assemble): Add handler for unsupported_rsp_register and invalid_src_register_set. (check_APX_operands): Add invalid check for push2/pop2. (match_template): Handle check_APX_operands. * testsuite/gas/i386/i386.exp: Add apx-push2pop2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2.d: New test. * testsuite/gas/i386/x86-64-apx-push2pop2.s: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Added bad testcases for POP2. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-reg.h: Add REG_EVEX_MAP4_8F. * i386-dis-evex-w.h: Add EVEX_W_MAP4_8F_R_0 and EVEX_W_MAP4_FF_R_6 * i386-dis-evex.h: Add REG_EVEX_MAP4_8F. * i386-dis.c (PUSH2_POP2_Fixup): Add special handling for PUSH2/POP2. (get_valid_dis386): Add handler for vector length and address_mode for APX-Push2/Pop2 insn. (nd): define nd as b for EVEX-promoted instrutions. (OP_VEX): Add handler of 64-bit vvvv register for APX-Push2/Pop2 insn. * i386-gen.c: Add Push2Pop2 bitfield. * i386-opc.h: Regenerated. * i386-opc.tbl: Regenerated.
2023-12-28Support APX NDDkonglin11-62/+62
opcodes/ChangeLog: * opcodes/i386-dis-evex-reg.h: Handle for REG_EVEX_MAP4_80, REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, REG_EVEX_MAP4_F6, REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, REG_EVEX_MAP4_FF. * opcodes/i386-dis-evex.h: Add NDD insn. * opcodes/i386-dis.c (nd): New define. (VexGb): Ditto. (VexGv): Ditto. (get_valid_dis386): Change for NDD decode. (print_insn): Ditto. (putop): Ditto. (intel_operand_size): Ditto. (OP_E_memory): Ditto. (OP_VEX): Ditto. * opcodes/i386-opc.h (VexVVVV_DST): New. * opcodes/i386-opc.tbl: Add APX NDD instructions and adjust VexVVVV. * opcodes/i386-tbl.h: Regenerated. gas/ChangeLog: * gas/config/tc-i386.c (operand_size_match): Support APX NDD that the number of operands is 3. (build_apx_evex_prefix): Change for ndd encode. (process_operands): Ditto. (build_modrm_byte): Ditto. (match_template): Support swap the first two operands for APX NDD. * testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd. * testsuite/gas/i386/x86-64-apx-ndd.d: New test. * testsuite/gas/i386/x86-64-apx-ndd.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili1-47/+47
This patch adds non-ND, non-NF forms of EVEX promotion insn. EVEX extension of legacy instructions: All promoted legacy instructions are placed in EVEX map 4, which is currently reserved. EVEX extension of EVEX instructions: All existing EVEX instructions are extended by APX using the extended EVEX prefix, so that they can access all 32 GPRs. EVEX extension of VEX instructions: Promoting a VEX instruction into the EVEX space does not change the map id, the opcode, or the operand encoding of the VEX instruction. Note: The promoted versions of MOVBE will be extended to include the “MOVBE reg1, reg2”. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (struct _i386_insn): Add has_egpr. (need_evex_encoding): Adjusted for apx. (cpu_flags_match): Ditto. (install_template): Handled APX combines. (is_apx_evex_encoding): Test apx evex encoding. (build_apx_evex_prefix): Enabe APX evex prefix. (md_assemble): Handle apx with evex encoding. (process_suffix): Handle apx map4 prefix. (check_register): Assign i.vec_encoding for APX evex instructions. * testsuite/gas/i386/x86-64-evex.d: Adjust test cases. * testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe. opcodes/ChangeLog: * i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3. * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0, PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD, PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF, PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1, PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8. * i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0. * i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn promote to apx to use gpr32 * opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90, X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2, X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91. * i386-dis.c (struct instr_info): Deleted bool r. (PREFIX_NP_OR_DATA): New. (NO_PREFIX): New. (putop): Ditto. (X86_64_EVEX_FROM_VEX_TABLE): Diito. (get_valid_dis386): Decode insn erex in extend evex prefix. Handle EVEX_MAP4 (print_insn): Handle PREFIX_DATA_AND_NP_ONLY. (print_register): Handle apx instructions decode. (OP_E_memory): Diito. (OP_G): Diito. (OP_XMM): Diito. (DistinctDest_Fixup): Diito. * i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4. * i386-opc.h (SPACE_EVEXMAP4): Add legacy insn promote to evex. * i386-opc.tbl: Handle some legacy and vex insns don't support gpr32. And add some legacy insn (map2 / 3) promote to evex.
2023-12-28Created an empty EVEX_MAP4_ sub-table for EVEX instructions.Cui, Lili1-0/+291
opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-08-02Revert "2.41 Release sources"Sam James1-30/+30
This reverts commit 675b9d612cc59446e84e2c6d89b45500cb603a8d. See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton1-30/+30
2023-07-11x86: misc further register-only insns don't need to go through mod_table[]Jan Beulich1-1/+1
Several already use OP_R(), which rejects the memory forms of insns, and a few others can easily be converted to do so as well. Note that for it to be able to use BadOp() without forward declaration, OP_Skip_MODRM() is moved down. While there add the previously missing PREFIX_OPCODE to legacy opcode 0FD7.
2023-07-11x86: slightly rework handling of some register-only insnsJan Beulich1-1/+1
Fold OP_MS() and OP_XS() into OP_R(), paralleling OP_M(). Use operand names (largely) matching those in the SDM. For 128-bit-only forms use Uxmm though, marking 256-bit forms as bad. This then allows no longer going through vex_len_table[] for two of the insns. Specifically _do not_ continue to mis-use v_mode.
2023-07-11x86: misc further memory-only insns don't need to go through mod_table[]Jan Beulich1-6/+6
Several already use OP_M(), which rejects the register forms of insns, and a few others can easily be converted to do so as well. (Note that FXSAVE_Fixup() wires through to OP_M(). Note further that OP_IndirE(), which wasn't placed very well anyway, is moved down to avoid the need to forward-declare BadOp().) Also adjust formatting of and drop PREFIX_OPCODE from a few adjacent entries.
2023-07-11x86: {,V}MOVNT* don't need to go through mod_table[]Jan Beulich1-1/+1
Most of them use Mx already for the memory operand, which rejects the register form of the insn. Use that operand type also for the two EVEX forms which so far have used EXEvexXNoBcst (and thus failed to reject the register forms), compensating by flagging broadcast as bad for all Mx. This way several other insns which don't permit embedded broadcast either are also covered at the same time.
2023-07-11x86: fold legacy/VEX {,V}MOV{H,L}* entriesJan Beulich1-2/+2
By changing decode order to do ModR/M.mod last (rather than VEX.L), the VEX entries (which are already reused by EVEX decoding) can be folded with their legacy counterparts as well. Note how this change of decode order also allows removing two auxiliary #define-s, which were introduced during earlier folding (because of that unhelpful order of steps).
2023-07-11x86: fold certain legacy/VEX table entriesJan Beulich1-12/+12
Introduce macro V to expand to 'v' in the VEX/EVEX case, and replace a couple of abort()s where legacy code can now legitimately make it. While there for {,V}LDDQU drop hoing through mod_table[] - OP_M() rejects register operands quite fine.
2023-07-04x86: flag bad EVEX masking for miscellaneous insnsJan Beulich1-7/+7
Masking is not permitted for certain further insns, not falling in any of the earlier categories. Introduce the Y macro (not expanding to any output) to flag such cases. Note that in a few cases entries already covered otherwise are converted as well, to continue to allow sharing of the string literals.
2022-11-02Support Intel AVX-IFMAHongyu Wang1-2/+2
x86: Support Intel AVX-IFMA Intel AVX IFMA instructions are marked with CpuVEX_PREFIX, which is cleared by default. Without {vex} pseudo prefix, Intel IFMA instructions are encoded with EVEX prefix. {vex} pseudo prefix will turn on VEX encoding for Intel IFMA instructions. gas/ * NEWS: Support Intel AVX-IFMA. * config/tc-i386.c (cpu_arch): Add avx_ifma. * doc/c-i386.texi: Document .avx_ifma. * testsuite/gas/i386/avx-ifma.d: New file. * testsuite/gas/i386/avx-ifma-intel.d: Likewise. * testsuite/gas/i386/avx-ifma.s: Likewise. * testsuite/gas/i386/x86-64-avx-ifma.d: Likewise. * testsuite/gas/i386/x86-64-avx-ifma-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-ifma.s: Likewise. * testsuite/gas/i386/i386.exp: Run AVX IFMA tests. opcodes/ * i386-dis.c (PREFIX_VEX_0F38B4): New. (PREFIX_VEX_0F38B5): Likewise. (VEX_W_0F38B4_P_2): Likewise. (VEX_W_0F38B5_P_2): Likewise. (prefix_table): Add PREFIX_VEX_0F38B4 and PREFIX_VEX_0F38B5. (vex_table): Add VEX_W_0F38B4_P_2 and VEX_W_0F38B5_P_2. * i386-dis-evex.h: Fold AVX512IFMA entries to AVX-IFMA. * i386-gen.c (cpu_flag_init): Clear the CpuAVX_IFMA bit in CPU_UNKNOWN_FLAGS. Add CPU_AVX_IFMA_FLGAS and CPU_ANY_AVX_IFMA_FLAGS. Add CpuAVX_IFMA to CPU_AVX2_FLAGS. (cpu_flags): Add CpuAVX_IFMA. * i386-opc.h (CpuAVX_IFMA): New. (i386_cpu_flags): Add cpuavx_ifma. * i386-opc.tbl: Add Intel AVX IFMA instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2022-10-24x86: emit {evex} prefix when disassembling ambiguous AVX512VL insnsJan Beulich1-87/+87
When no AVX512-specific functionality is in use, the disassembly of AVX512VL insns is indistinguishable from their AVX counterparts (if such exist). Emit the {evex} pseudo-prefix in such cases. Where applicable drop stray uses of PREFIX_OPCODE from table entries.
2022-10-17x86: fold AVX512-VNNI disassembler entries with AVX-VNNI onesJan Beulich1-2/+2
Make %XV also print the separating blank in the VEX case, while making it do nothing for EVEX-encoded insns. This way the AVX-VNNI entries can be re-used for AVX512-VNNI, at the same time fixing the lack of EVEX.W decoding. For the AVX-VNNI ones further make sure only VEX.66 forms are actually decoded.
2022-01-14x86: share yet more VEX table entries with EVEX decodingJan Beulich1-16/+16
On top of prior similar work more opportunities have appeared in the meantime. Note that this also happens to address the prior lack of decoding of EVEX.L'L for VMOV{L,H}P{S,D} and VMOV{LH,HL}PS.
2022-01-14x86: consistently use scalar_mode for AVX512-FP16 scalar insnsJan Beulich1-16/+16
For some reason the original AVFX512F insns were not taken as a basis here, causing unnecessary divergence. While not an active issue, it is still relevant to note that OP_XMM() has special treatment of e.g. scalar_mode (marking broadcast as invalid). Such would better be consistent for all sufficiently similar insns.
2022-01-14x86: reduce AVX512 FP set of insns decoded through vex_w_table[]Jan Beulich1-4/+4
Like for AVX512-FP16, there's not that many FP insns where going through this table is easier / cheaper than using suitable macros. Utilize %XS and %XD more to eliminate a fair number of table entries. While doing this I noticed a few anomalies. Where lines get touched / moved anyway, these are being addressed right here: - vmovshdup used EXx for its 2nd operand, thus displaying seemingly valid broadcast when EVEX.b is set with a memory operand; use EXEvexXNoBcst instead just like vmovsldup already does - vmovlhps used EXx for its 3rd operand, when all sibling entries use EXq; switch to EXq there for consistency (the two differ only for memory operands)
2022-01-14x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[]Jan Beulich1-5/+5
Like already indicated during review of the original submission, there's really only very few insns where going through this table is easier / cheaper than using suitable macros. Utilize %XH more and introduce similar %XS and %XD (which subsequently can be used for further table size reduction). While there also switch to using oappend() in 'XH' macro processing.
2021-08-05[PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili1-13/+595
Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32 in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx). There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8 operands predated our current conventions; those instructions moved to map 3. FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3 is very sparsely populated. Most of the FP16 instructions share opcodes and prefix (EVEX.pp) bits with the related FP32 operations. Intel AVX512 FP16 instructions has new displacements scaling rules, please refer to the public software developer manual for detail information. gas/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (struct Broadcast_Operation): Adjust comment. (cpu_arch): Add .avx512_fp16. (cpu_noarch): Add noavx512_fp16. (pte): Add evexmap5 and evexmap6. (build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6. (check_VecOperations): Handle {1to32}. (check_VecOperands): Handle CheckRegNumb. (check_word_reg): Handle Toqword. (i386_error): Add invalid_dest_and_src_register_set. (match_template): Handle invalid_dest_and_src_register_set. * doc/c-i386.texi: Document avx512_fp16, noavx512_fp16. opcodes/ 2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com> H.J. Lu <hongjiu.lu@intel.com> Wei Xiao <wei3.xiao@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (EXwScalarS): New. (EXxh): Ditto. (EXxhc): Ditto. (EXxmmqh): Ditto. (EXxmmqdh): Ditto. (EXEvexXwb): Ditto. (DistinctDest_Fixup): Ditto. (enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode and w_swap_mode. (enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C, PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1, PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79, PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C, PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56, PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7 (enum): Add EVEX_MAP5 and EVEX_MAP6. (enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B, EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0, EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3, EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2, EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2, (get_valid_dis386): Properly handle new instructions. (intel_operand_size): Handle new modes. (OP_E_memory): Ditto. (OP_EX): Ditto. * i386-dis-evex.h: Updated for AVX512_FP16. * i386-dis-evex-mod.h: Updated for AVX512_FP16. * i386-dis-evex-prefix.h: Updated for AVX512_FP16. * i386-dis-evex-reg.h : Updated for AVX512_FP16. * i386-dis-evex-w.h : Updated for AVX512_FP16. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS, and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS and CPU_ANY_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512_FP16. (opcode_modifiers): Add DistinctDest. * i386-opc.h (enum): (AVX512_FP16): New. (i386_opcode_modifier): Add reqdistinctreg. (i386_cpu_flags): Add cpuavx512_fp16. (EVEXMAP5): Defined as a macro. (EVEXMAP6): Ditto. * i386-opc.tbl: Add Intel AVX512_FP16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Ditto.
2021-07-22x86: drop vex_scalar_w_dq_modeJan Beulich1-21/+21
It has only a single use and can easily be represented by dq_mode instead. Plus its handling in intel_operand_size() was duplicating that of vex_vsib_{d,q}_w_dq_mode anyway.
2021-07-22x86: drop OP_Mask()Jan Beulich1-11/+11
By moving its vex.r check there it becomes fully redundant with OP_G().
2021-03-25x86: flag bad S/G insn operand combinationsJan Beulich1-2/+2
For VEX-encoded ones, all three involved vector registers have to be distinct. For EVEX-encoded ones an actual mask register has to be in use and zeroing-masking cannot be used (violation of either will #UD). Additionally both involved vector registers have to be distinct for EVEX-encoded gathers.
2021-03-10x86/Intel: correct AVX512 S/G disassemblyJan Beulich1-4/+4
Commit 6ff00b5e12e7 ("x86/Intel: correct permitted operand sizes for AVX512 scatter/gather") brought the assembler side of AVX512 S/G insn handling in line with AVX2's, but the disassembler side was forgotten. This has the benefit of - allowing to fold a number of table entries, - rendering a few #define-s and enumerators unused.
2021-03-10x86: reuse further VEX entries for EVEXJan Beulich1-10/+10
When the VEX.L=1 decode matches that of both EVEX.L'L=1 and EVEX.L'L=2 (typically when all three are invalid) the (smaller) VEX table entry can be reused by EVEX, instead of duplicating data. (Note that XM and XMM as well as EXxmm_md and EXd are equivalent at least for the purposes here.)
2021-03-10x86: reuse VEX entries for EVEX vperm{q,pd}Jan Beulich1-2/+2
By matching VEX decode order (L before W), some EVEX entries can refer back to VEX ones instead of carrying duplicates.
2021-03-10x86: re-arrange order of decode for various EVEX opcodesJan Beulich1-17/+17
The order of decodes influences the overall number of table entries. Reduce table size quite a bit by first decoding few-alternatives attributes common to all valid leaves. This also adds a PREFIX_DATA 7531c61332db ("x86: simplify decode of opcodes valid with (embedded) 66 prefix only") missed to apply to vbroadcastf64x4.
2020-07-14x86: drop Rdq, Rd, and MaskRJan Beulich1-1/+1
Rdq, Rd, and MaskR can be replaced by Edq, Ed / Rm, and MaskE respectively, as OP_R() doesn't enforce ModRM.mod == 3, and hence where MOD matters but hasn't been decoded yet it needs to be anyway. (The case of converting to Rm is temporary until a subsequent change.)
2020-07-14x86: simplify decode of opcodes valid with (embedded) 66 prefix onlyJan Beulich1-217/+217
The only valid (embedded or explicit) prefix being the data size one (which is a fairly common pattern), avoid going through prefix_table[]. Instead extend the "required prefix" logic to also handle PREFIX_DATA alone in a table entry, now used to identify this case. This requires moving the (adjusted) ->prefix_requirement logic ahead of the printing of stray prefixes, as the latter needs to observe the new setting of PREFIX_DATA in used_prefixes. Also add PREFIX_OPCODE on related entries when previously there was mistakenly no decode step through prefix_table[].
2020-07-14x86: drop further EVEX table entries that can be served by VEX onesJan Beulich1-4/+4
A few cases were missed by 6df22cf64c93 ("x86: drop EVEX table entries that can be served by VEX ones").
2020-07-06x86: drop EVEX table entries that can be made served by VEX onesJan Beulich1-15/+15
By doing the EVEX.W decode first, in various cases VEX table entries can be re-used.
2020-07-06x86: honor VEX.W for VCVT{PH2PS,PS2PH}Jan Beulich1-1/+1
Unlike for the EVEX-encoded versions, the VEX ones failed to decode VEX.W. Once the necessary adjustments are done, it becomes obvious that the EVEX and VEX table entries for VCVTPS2PH are identical and can hence be folded.
2020-07-06x86: drop EVEX table entries that can be served by VEX onesJan Beulich1-80/+80
The duplication is not only space inefficient, but also risks entries going out of sync (some of which that I became aware of while doing this work will get addressed subsequently). Right here note that for VGF2P8MULB this also addresses the prior lack of EVEX.W decoding (i.e. a first example of out of sync entries). This introduces EXxEVexR to some VEX templates, on the basis that this operand is benign there and only relevant when EVEX encoding ends up reaching these entries.
2020-06-09x86: utilize X macro in EVEX decodingJan Beulich1-12/+12
For major opcodes allowing only packed FP kinds of operands, i.e. the ones where legacy and AVX decoding uses the X macro, we can do so for AVX512 as well, by attaching to the checking logic the "EVEX.W must match presence of embedded 66 prefix" rule. (Encodings not following this general pattern simply may not gain the PREFIX_OPCODE attribute.) Note that testing of the thus altered decoding has already been put in place by "x86: correct decoding of packed-FP-only AVX encodings". This can also be at least partly applied to scalar-FP-only insns (i.e. V{,U}COMIS{S,D}) as well as the vector-FP forms of insns also allowing scalar encodings (e.g. VADDP{S,D}). Take the opportunity and also fix EVEX-encoded VMOVNTP{S,D} as well as to-memory forms of VMOV{L,H}PS and both forms of VMOV{L,H}PD to wrongly disassemble with only register operands.
2019-06-21i386: Break i386-dis-evex.h into small filesH.J. Lu1-3467/+0
Break i386-dis-evex.h into small files such that each file is included just once. * i386-dis-evex.h: Break into ... * i386-dis-evex-len.h: New file. * i386-dis-evex-mod.h: Likewise. * i386-dis-evex-prefix.h: Likewise. * i386-dis-evex-reg.h: Likewise. * i386-dis-evex-w.h: Likewise. * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h, i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and i386-dis-evex-mod.h.
2019-06-19i386: Check vector length for EVEX broadcast instructionsH.J. Lu1-10/+80
Since not all vector lengths are supported by EVEX broadcast instructions, decode them only with supported vector lengths. gas/ PR binutils/24700 * testsuite/gas/i386/disassem.s: Add test for vbroadcasti32x8 with invalid vector length. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24700 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and EVEX_W_0F385B_P_2. (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0, EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and EVEX_LEN_0F385B_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum. (EVEX_LEN_0F3819_P_2_W_1): Likewise. (EVEX_LEN_0F381A_P_2_W_0): Likewise. (EVEX_LEN_0F381A_P_2_W_1): Likewise. (EVEX_LEN_0F381B_P_2_W_0): Likewise. (EVEX_LEN_0F381B_P_2_W_1): Likewise. (EVEX_LEN_0F385A_P_2_W_0): Likewise. (EVEX_LEN_0F385A_P_2_W_1): Likewise. (EVEX_LEN_0F385B_P_2_W_0): Likewise. (EVEX_LEN_0F385B_P_2_W_1): Likewise.
2019-06-17i386: Check vector length for vshufXXX/vinsertXXX/vextractXXXH.J. Lu1-12/+96
Since not all vector lengths are supported by vshufXXX, vinsertXXX and vextractXXX, decode them only with supported vector lengths. gas/ PR binutils/24691 * testsuite/gas/i386/disassem.s: Add test for vshuff32x4 with invalid vector length. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24691 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2. (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and EVEX_LEN_0F3A43_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum. (EVEX_LEN_0F3A23_P_2_W_1): Likewise. (EVEX_LEN_0F3A38_P_2_W_0): Likewise. (EVEX_LEN_0F3A38_P_2_W_1): Likewise. (EVEX_LEN_0F3A39_P_2_W_0): Likewise. (EVEX_LEN_0F3A39_P_2_W_1): Likewise. (EVEX_LEN_0F3A3A_P_2_W_0): Likewise. (EVEX_LEN_0F3A3A_P_2_W_1): Likewise. (EVEX_LEN_0F3A3B_P_2_W_0): Likewise. (EVEX_LEN_0F3A3B_P_2_W_1): Likewise. (EVEX_LEN_0F3A43_P_2_W_0): Likewise. (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
2019-06-05i386: Check vector length for EVEX vextractfXX and vinsertfXXH.J. Lu1-8/+64
Since not all vector lengths are supported by EVEX vextractfXX and vinsertfXX, decode them only with supported vector lengths. gas/ PR binutils/24633 * testsuite/gas/i386/disassem.s: Add tests for invalid vector lengths for EVEX vextractfXX and vinsertfXX. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24633 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2. (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0, EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0, EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0, EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0, EVEX_LEN_0F3A1B_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum. (EVEX_LEN_0F3A18_P_2_W_1): Likewise. (EVEX_LEN_0F3A19_P_2_W_0): Likewise. (EVEX_LEN_0F3A19_P_2_W_1): Likewise. (EVEX_LEN_0F3A1A_P_2_W_0): Likewise. (EVEX_LEN_0F3A1A_P_2_W_1): Likewise. (EVEX_LEN_0F3A1B_P_2_W_0): Likewise. (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu1-1/+13
This patch enables support for VP2INTERSECT in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for VP2INTERSECT details. Make check-gas is ok. gas/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect. (cpu_noarch): Likewise. * doc/c-i386.texi: Document avx512_vp2intersect. * testsuite/gas/i386/i386.exp: Run vp2intersect tests. * testsuite/gas/i386/vp2intersect-intel.d: New test. * testsuite/gas/i386/vp2intersect.d: Likewise. * testsuite/gas/i386/vp2intersect.s: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise. opcodes/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3. * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT instructions. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS, CPU_ANY_AVX512_VP2INTERSECT_FLAGS. (cpu_flags): Add CpuAVX512_VP2INTERSECT. * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT. (i386_cpu_flags): Add cpuavx512_vp2intersect. * i386-opc.tbl: Add AVX512_VP2INTERSECT insns. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
generated by cgit v1.1 at 2024-07-13 10:47:21 +0000