| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-06-10 | x86: disassembler macro for condition code | Jan Beulich | 1 | -109/+4 |
| 2024-05-22 | Support APX zero-upper | Cui, Lili | 1 | -0/+112 |
| 2024-04-03 | x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4 | Cui, Lili | 1 | -35/+0 |
| 2024-01-19 | x86: support APX forms of U{RD,WR}MSR | Jan Beulich | 1 | -2/+2 |
| 2023-12-28 | Support APX GPR32 with extend evex prefix | Cui, Lili | 1 | -0/+58 |
| 2023-08-02 | Revert "2.41 Release sources" | Sam James | 1 | -11/+11 |
| 2023-08-02 | 2.41 Release sourcesbinutils-2_41-release | Nick Clifton | 1 | -11/+11 |
| 2023-07-11 | x86: various operations on mask registers can avoid going through mod_table[] | Jan Beulich | 1 | -4/+4 |
| 2023-07-04 | x86: flag bad EVEX masking for miscellaneous insns | Jan Beulich | 1 | -9/+9 |
| 2022-10-24 | x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns | Jan Beulich | 1 | -24/+24 |
| 2022-10-17 | x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insns | Jan Beulich | 1 | -6/+6 |
| 2022-10-17 | x86: fold AVX512-VNNI disassembler entries with AVX-VNNI ones | Jan Beulich | 1 | -2/+2 |
| 2022-01-14 | x86: share yet more VEX table entries with EVEX decoding | Jan Beulich | 1 | -90/+0 |
| 2022-01-14 | x86: consistently use scalar_mode for AVX512-FP16 scalar insns | Jan Beulich | 1 | -15/+15 |
| 2022-01-14 | x86: reduce AVX512 FP set of insns decoded through vex_w_table[] | Jan Beulich | 1 | -35/+35 |
| 2022-01-14 | x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[] | Jan Beulich | 1 | -39/+30 |
| 2021-08-05 | [PATCH 1/2] Enable Intel AVX512_FP16 instructions | Cui,Lili | 1 | -0/+221 |
| 2021-07-22 | x86: drop vex_scalar_w_dq_mode | Jan Beulich | 1 | -2/+2 |
| 2021-07-22 | x86: drop xmm_m{b,w,d,q}_mode | Jan Beulich | 1 | -4/+4 |
| 2021-07-22 | x86: correct VCVT{,U}SI2SD rounding mode handling | Jan Beulich | 1 | -2/+2 |
| 2021-07-22 | x86: drop OP_Mask() | Jan Beulich | 1 | -9/+9 |
| 2021-03-10 | x86: reuse further VEX entries for EVEX | Jan Beulich | 1 | -2/+2 |
| 2020-07-14 | x86: drop Rdq, Rd, and MaskR | Jan Beulich | 1 | -2/+2 |
| 2020-07-14 | x86: simplify decode of opcodes valid with (embedded) 66 prefix only | Jan Beulich | 1 | -918/+0 |
| 2020-07-14 | x86: drop further EVEX table entries that can be served by VEX ones | Jan Beulich | 1 | -26/+0 |
| 2020-07-14 | x86: replace %LW by %DQ | Jan Beulich | 1 | -41/+41 |
| 2020-07-14 | x86: extend %BW use to VP{COMPRESS,EXPAND}{B,W} | Jan Beulich | 1 | -2/+2 |
| 2020-07-14 | x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel mode | Jan Beulich | 1 | -2/+2 |
| 2020-07-14 | x86: fold VCMP_Fixup() into CMP_Fixup() | Jan Beulich | 1 | -2/+2 |
| 2020-07-07 | x86: introduce %BW to avoid going through vex_w_table[] | Jan Beulich | 1 | -11/+11 |
| 2020-07-06 | x86: use %LW / %XW instead of going through vex_w_table[] | Jan Beulich | 1 | -15/+15 |
| 2020-07-06 | x86: drop EVEX table entries that can be made served by VEX ones | Jan Beulich | 1 | -90/+0 |
| 2020-07-06 | x86: AVX512 VPERM{D,Q,PS,PD} insns need to honor EVEX.L'L | Jan Beulich | 1 | -2/+2 |
| 2020-07-06 | x86: AVX512 extract/insert insns need to honor EVEX.L'L | Jan Beulich | 1 | -8/+8 |
| 2020-07-06 | x86: honor VEX.W for VCVT{PH2PS,PS2PH} | Jan Beulich | 1 | -6/+0 |
| 2020-07-06 | x86: drop EVEX table entries that can be served by VEX ones | Jan Beulich | 1 | -480/+0 |
| 2020-06-09 | x86: utilize X macro in EVEX decoding | Jan Beulich | 1 | -98/+26 |
| 2020-01-31 | x86: replace EXxmm_mdq by EXVexWdqScalar | Jan Beulich | 1 | -20/+20 |
| 2019-07-01 | x86: add missing pseudo ops for VPCLMULQDQ ISA extension | Jan Beulich | 1 | -1/+1 |
| 2019-07-01 | x86: remove ModRM.mod decoding layer from AVX512F VMOVS{S,D} | Jan Beulich | 1 | -4/+4 |
| 2019-06-27 | i386: Check vector length for scatter/gather prefetch instructions | H.J. Lu | 1 | -4/+4 |
| 2019-06-25 | x86: drop dqa_mode | Jan Beulich | 1 | -2/+2 |
| 2019-06-21 | i386: Break i386-dis-evex.h into small files | H.J. Lu | 1 | -0/+1969 |
