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path: root/opcodes/i386-dis-evex-prefix.h
AgeCommit message (Expand)AuthorFilesLines
7 daysSupport APX CFCMOVCui, Lili1-2/+2
2024-06-10x86: disassembler macro for condition codeJan Beulich1-109/+4
2024-05-22Support APX zero-upperCui, Lili1-0/+112
2024-04-03x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4Cui, Lili1-35/+0
2024-01-19x86: support APX forms of U{RD,WR}MSRJan Beulich1-2/+2
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili1-0/+58
2023-08-02Revert "2.41 Release sources"Sam James1-11/+11
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton1-11/+11
2023-07-11x86: various operations on mask registers can avoid going through mod_table[]Jan Beulich1-4/+4
2023-07-04x86: flag bad EVEX masking for miscellaneous insnsJan Beulich1-9/+9
2022-10-24x86: emit {evex} prefix when disassembling ambiguous AVX512VL insnsJan Beulich1-24/+24
2022-10-17x86: properly decode EVEX.W for AVX512_4{FMAPS,VNNIW} insnsJan Beulich1-6/+6
2022-10-17x86: fold AVX512-VNNI disassembler entries with AVX-VNNI onesJan Beulich1-2/+2
2022-01-14x86: share yet more VEX table entries with EVEX decodingJan Beulich1-90/+0
2022-01-14x86: consistently use scalar_mode for AVX512-FP16 scalar insnsJan Beulich1-15/+15
2022-01-14x86: reduce AVX512 FP set of insns decoded through vex_w_table[]Jan Beulich1-35/+35
2022-01-14x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[]Jan Beulich1-39/+30
2021-08-05[PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili1-0/+221
2021-07-22x86: drop vex_scalar_w_dq_modeJan Beulich1-2/+2
2021-07-22x86: drop xmm_m{b,w,d,q}_modeJan Beulich1-4/+4
2021-07-22x86: correct VCVT{,U}SI2SD rounding mode handlingJan Beulich1-2/+2
2021-07-22x86: drop OP_Mask()Jan Beulich1-9/+9
2021-03-10x86: reuse further VEX entries for EVEXJan Beulich1-2/+2
2020-07-14x86: drop Rdq, Rd, and MaskRJan Beulich1-2/+2
2020-07-14x86: simplify decode of opcodes valid with (embedded) 66 prefix onlyJan Beulich1-918/+0
2020-07-14x86: drop further EVEX table entries that can be served by VEX onesJan Beulich1-26/+0
2020-07-14x86: replace %LW by %DQJan Beulich1-41/+41
2020-07-14x86: extend %BW use to VP{COMPRESS,EXPAND}{B,W}Jan Beulich1-2/+2
2020-07-14x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel modeJan Beulich1-2/+2
2020-07-14x86: fold VCMP_Fixup() into CMP_Fixup()Jan Beulich1-2/+2
2020-07-07x86: introduce %BW to avoid going through vex_w_table[]Jan Beulich1-11/+11
2020-07-06x86: use %LW / %XW instead of going through vex_w_table[]Jan Beulich1-15/+15
2020-07-06x86: drop EVEX table entries that can be made served by VEX onesJan Beulich1-90/+0
2020-07-06x86: AVX512 VPERM{D,Q,PS,PD} insns need to honor EVEX.L'LJan Beulich1-2/+2
2020-07-06x86: AVX512 extract/insert insns need to honor EVEX.L'LJan Beulich1-8/+8
2020-07-06x86: honor VEX.W for VCVT{PH2PS,PS2PH}Jan Beulich1-6/+0
2020-07-06x86: drop EVEX table entries that can be served by VEX onesJan Beulich1-480/+0
2020-06-09x86: utilize X macro in EVEX decodingJan Beulich1-98/+26
2020-01-31x86: replace EXxmm_mdq by EXVexWdqScalarJan Beulich1-20/+20
2019-07-01x86: add missing pseudo ops for VPCLMULQDQ ISA extensionJan Beulich1-1/+1
2019-07-01x86: remove ModRM.mod decoding layer from AVX512F VMOVS{S,D}Jan Beulich1-4/+4
2019-06-27i386: Check vector length for scatter/gather prefetch instructionsH.J. Lu1-4/+4
2019-06-25x86: drop dqa_modeJan Beulich1-2/+2
2019-06-21i386: Break i386-dis-evex.h into small filesH.J. Lu1-0/+1969
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