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path: root/opcodes/aarch64-opc-2.c
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2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford1-0/+6
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li1-2/+2
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy1-53/+57
2016-11-18[AArch64] Add ARMv8.3 weaker release consistency load instructionsSzabolcs Nagy1-18/+18
2016-11-18[AArch64] Add ARMv8.3 javascript floating-point conversion instructionSzabolcs Nagy1-25/+25
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy1-15/+16
2016-11-11[AArch64] Add ARMv8.3 combined pointer authentication branch instructionsSzabolcs Nagy1-52/+52
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy1-26/+27
2016-11-11[AArch64] Add ARMv8.3 single source PAC instructionsSzabolcs Nagy1-49/+49
2016-11-11[AArch64] Add ARMv8.3 instructions which are in the NOP spaceSzabolcs Nagy1-10/+10
2016-09-21[AArch64][SVE 31/32] Add SVE instructionsRichard Sandiford1-0/+11
2016-09-21[AArch64][SVE 29/32] Add new SVE core & FP register operandsRichard Sandiford1-0/+6
2016-09-21[AArch64][SVE 28/32] Add SVE FP immediate operandsRichard Sandiford1-0/+4
2016-09-21[AArch64][SVE 27/32] Add SVE integer immediate operandsRichard Sandiford1-0/+18
2016-09-21[AArch64][SVE 26/32] Add SVE MUL VL addressing modesRichard Sandiford1-0/+6
2016-09-21[AArch64][SVE 25/32] Add support for SVE addressing modesRichard Sandiford1-0/+31
2016-09-21[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALEDRichard Sandiford1-0/+1
2016-09-21[AArch64][SVE 23/32] Add SVE pattern and prfop operandsRichard Sandiford1-0/+2
2016-09-21[AArch64][SVE 21/32] Add Zn and Pn registersRichard Sandiford1-0/+18
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-12-14[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instru...Matthew Wahab1-43/+43
2015-12-14[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.Matthew Wahab1-45/+45
2015-12-14[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.Matthew Wahab1-43/+43
2015-12-14[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.Matthew Wahab1-37/+37
2015-12-14[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.Matthew Wahab1-53/+53
2015-12-14[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.Matthew Wahab1-44/+44
2015-12-14[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.Matthew Wahab1-53/+53
2015-12-14[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.Matthew Wahab1-56/+56
2015-12-14[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.Matthew Wahab1-56/+56
2015-12-14[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.Matthew Wahab1-50/+50
2015-12-14[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.Matthew Wahab1-57/+57
2015-12-11[AArch64][Patch 5/5] Add instruction PSB CSYNCMatthew Wahab1-0/+1
2015-12-11[AArch64][Patch 4/5] Support HINT aliases taking operands.Matthew Wahab1-2/+2
2015-11-27[AArch64][PATCH 3/3] Add floating-point FP16 instructionsMatthew Wahab1-34/+34
2015-11-27[AArch64] Add ARMv8.2 instruction alias REV64.Matthew Wahab1-18/+18
2015-11-27[AArch64] Add ARMv8.2 instructions BFC and REV64.Matthew Wahab1-27/+28
2015-06-02[AArch64] Support for ARMv8.1a Adv.SIMD instructionsMatthew Wahab1-54/+54
2015-06-02[AArch64] Support for ARMv8.1a Limited Ordering Regions extensionMatthew Wahab1-12/+12
2015-03-10[AARCH64] Remove Load/Store register (unscaled immediate) alias.Jiong Wang1-19/+19
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-09-03[PATCH/AArch64] Implement LSE featureJiong Wang1-5/+6
2014-03-05Update copyright yearsAlan Modra1-1/+1
2013-11-05gas/Yufeng Zhang1-1/+2
2013-02-28include/opcode/Yufeng Zhang1-33/+33
2013-01-30include/opcode/Yufeng Zhang1-47/+50
2012-08-13Add support for 64-bit ARM architecture: AArch64Nick Clifton1-0/+195
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