| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2017-05-30 | [ARC] Allow CPU to be enforced via disassemble_info options | Anton Kolesov | 1 | -0/+9 |
| 2017-05-24 | Move print_insn_XXX to an opcodes internal header | Yao Qi | 1 | -0/+28 |
| 2017-05-24 | Use disassemble.c:disassembler select rl78 disassembler | Yao Qi | 1 | -0/+5 |
| 2017-05-24 | Refactor disassembler selection | Yao Qi | 1 | -0/+5 |
| 2017-05-22 | x86: Add NOTRACK prefix support | H.J. Lu | 1 | -0/+16 |
| 2017-05-19 | binutils: support for the SPARC M8 processor | Jose E. Marchesi | 1 | -0/+37 |
| 2017-05-18 | Don't compare boolean values against TRUE or FALSE | Alan Modra | 1 | -0/+7 |
| 2017-05-15 | MIPS16e2: Add MIPS16e2 ASE support | Maciej W. Rozycki | 1 | -0/+28 |
| 2017-05-15 | MIPS/opcodes: Remove an incorrect MT ASE reference in MFC0/MTC0 decoding | Maciej W. Rozycki | 1 | -0/+5 |
| 2017-05-12 | MIPS16/opcodes: Make the handling of BREAK and SDBBP consistent | Maciej W. Rozycki | 1 | -0/+6 |
| 2017-05-12 | MIPS/opcodes: Mark descriptive SYNC mnemonics as aliases | Maciej W. Rozycki | 1 | -0/+8 |
| 2017-05-10 | [ARC] Object attributes. | Claudiu Zissulescu | 1 | -0/+7 |
| 2017-05-04 | RISC-V: Fix disassemble for c.li, c.andi and c.addiw | Kito Cheng | 1 | -0/+4 |
| 2017-05-02 | RISC-V: Change CALL macro to use ra as the temporary address register | Michael Clark | 1 | -0/+5 |
| 2017-05-02 | MIPS16/opcodes: Keep the LSB of PC-relative offsets in disassembly | Maciej W. Rozycki | 1 | -0/+5 |
| 2017-05-02 | Fix value in comment of disassembled ARM type A opcodes. | Bernd Edlinger | 1 | -0/+4 |
| 2017-04-25 | [ARC] Enhance enter/leave mnemonics. | Claudiu Zissulescu | 1 | -0/+7 |
| 2017-04-25 | [ARC] Prefer NOP instead of MOV 0,0 | Claudiu Zissulescu | 1 | -0/+4 |
| 2017-04-25 | MIPS16/opcodes: Add `-M no-aliases' disassembler option help text | Maciej W. Rozycki | 1 | -0/+5 |
| 2017-04-25 | MIPS16/opcodes: Annotate instruction aliases | Maciej W. Rozycki | 1 | -0/+6 |
| 2017-04-24 | Fix snafu in aarch64 opcodes debugging statement. | Tamar Christina | 1 | -0/+5 |
| 2017-04-22 | PowerPC VLE insn set additions | Alan Modra | 1 | -0/+8 |
| 2017-04-21 | opcodes: mark SPARC RETT instructions as v6notv9. | Jose E. Marchesi | 1 | -0/+4 |
| 2017-04-21 | Fix detection of illegal AArch64 opcodes that resemble LD1R, LD2R, LD3R and L... | Nick Clifton | 1 | -0/+6 |
| 2017-04-13 | Regen cgen files | Alan Modra | 1 | -0/+16 |
| 2017-04-11 | Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500 | Alan Modra | 1 | -1/+3 |
| 2017-04-11 | Bye bye PPC_OPCODE_HTM and -mhtm | Alan Modra | 1 | -2/+3 |
| 2017-04-11 | Bye Bye PPC_OPCODE_VSX3 | Alan Modra | 1 | -1/+4 |
| 2017-04-11 | Bye bye PPC_OPCODE_ALTIVEC2 | Alan Modra | 1 | -0/+6 |
| 2017-04-10 | Tidy ppc476 opcodes | Alan Modra | 1 | -0/+7 |
| 2017-04-10 | WebAssembly disassembler support | Pip Cet | 1 | -0/+5 |
| 2017-04-07 | Remove E6500 insns from PPC_OPCODE_ALTIVEC2 | Alan Modra | 1 | -0/+8 |
| 2017-04-06 | Add support for disassembling WebAssembly opcodes. | Pip Cet | 1 | -0/+11 |
| 2017-04-05 | -Wwrite-strings: Constify struct disassemble_info's disassembler_options field | Pedro Alves | 1 | -0/+7 |
| 2017-04-04 | RISC-V: Resurrect GP-relative disassembly hints | Palmer Dabbelt | 1 | -0/+5 |
| 2017-03-30 | Add support for the WebAssembly file format and the wasm32 ELF conversion to ... | Pip Cet | 1 | -0/+6 |
| 2017-03-29 | opcodes: sparc: support missing SPARC ASIs from UA2005, UA2007, OSA2011, & OS... | Jose E. Marchesi | 1 | -0/+6 |
| 2017-03-29 | PowerPC -Mraw disassembly | Alan Modra | 1 | -0/+9 |
| 2017-03-27 | PR21303, objdump doesn't show e200z4 insns | Alan Modra | 1 | -0/+6 |
| 2017-03-27 | Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions. | Rinat Zelig | 1 | -0/+10 |
| 2017-03-21 | S/390: Remove vx2 facility flag | Andreas Krebbel | 1 | -0/+5 |
| 2017-03-21 | arc/nps400: Add cp16/cp32 instructions to opcodes library | Rinat Zelig | 1 | -0/+9 |
| 2017-03-17 | E6500 spr mnemonics | Alan Modra | 1 | -0/+7 |
| 2017-03-15 | RISC-V: Fix assembler for c.li, c.andi and c.addiw | Kito Cheng | 1 | -0/+6 |
| 2017-03-15 | RISC-V: Fix assembler for c.addi, rd can be x0 | Kito Cheng | 1 | -0/+4 |
| 2017-03-14 | RISC-V: Fix [dis]assembly of srai/srli | Andrew Waterman | 1 | -0/+7 |
| 2017-03-09 | X86: Add pseudo prefixes to control encoding | H.J. Lu | 1 | -0/+10 |
| 2017-03-09 | Use CpuCET on rdsspq | H.J. Lu | 1 | -0/+5 |
| 2017-03-08 | Update -maltivec and -mvsx options to only enable their oldest instructions. | Peter Bergner | 1 | -0/+5 |
| 2017-03-08 | Add support for the new 'lnia' extended mnemonic. | Peter Bergner | 1 | -0/+4 |
