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| author | Kito Cheng <kito.cheng@gmail.com> | 2017-04-05 20:58:28 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2017-05-04 03:20:30 -0700 |
| commit | f91d48deb29d9e6f4b530f586db0140943ed0d83 (patch) | |
| tree | 41c3e2ccd3bc4a9c346d80196851f94c6b220ef4 /opcodes/ChangeLog | |
| parent | 45eba0ab7d26435121facb68847fbd0cd4a313c1 (diff) | |
| download | gdb-f91d48deb29d9e6f4b530f586db0140943ed0d83.zip gdb-f91d48deb29d9e6f4b530f586db0140943ed0d83.tar.gz gdb-f91d48deb29d9e6f4b530f586db0140943ed0d83.tar.bz2 | |
RISC-V: Fix disassemble for c.li, c.andi and c.addiw
ChangeLog
2017-05-03 Kito Cheng <kito.cheng@gmail.com>
* riscv-dis.c (print_insn_args): Handle 'Co' operands.
Diffstat (limited to 'opcodes/ChangeLog')
| -rw-r--r-- | opcodes/ChangeLog | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 355a162..ea0902f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2017-05-03 Kito Cheng <kito.cheng@gmail.com> + + * riscv-dis.c (print_insn_args): Handle 'Co' operands. + 2017-05-01 Michael Clark <michaeljclark@mac.com> * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary |