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AgeCommit message (Expand)AuthorFilesLines
2019-08-12Modify the ARM encoding and decoding of SQRSHRL and UQRSHLL MVE instructions.Srinath Parvathaneni1-0/+7
2019-08-07Prevent objdump from aborting when asked to disassemble an unknown type of AR...Phillipe Antoine1-0/+8
2019-08-07x86: drop stray FloatMFJan Beulich1-0/+7
2019-08-05Removes support in the ARM assembler for the unsigned variants of the VQ(R)DM...Barnaby Wilks1-0/+5
2019-07-30RISC-V: Fix minor issues with FP csr instructions.Jim Wilson1-0/+8
2019-07-24[ARC] Update disassembler opcode selectionClaudiu Zissulescu1-0/+7
2019-07-24[ARC] Update ARC opcode tableClaudiu Zissulescu1-0/+8
2019-07-23[AArch64] Add support for GMID_EL1 register for +memtagKyrylo Tkachov1-0/+5
2019-07-23Add Changelog entry missing from previous delta.Nick Clifton1-0/+5
2019-07-19cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassemblerJose E. Marchesi1-0/+4
2019-07-17x86: drop stale Mem enumeratorJan Beulich1-0/+8
2019-07-16x86: make RegMem an opcode modifierJan Beulich1-0/+23
2019-07-16x86: fold SReg{2,3}Jan Beulich1-0/+13
2019-07-15cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructionsJose E. Marchesi1-0/+6
2019-07-14cpu,opcodes,gas: fix arguments to ldabs and ldind eBPF instructionsJose E. Marchesi1-0/+5
2019-07-10arm-dis.c (print_insn_coprocessor): Rename index to index_operand.Hans-Peter Nilsson1-0/+5
2019-07-05Kito's 5-part patch set to improve .insn support.Jim Wilson1-0/+9
2019-07-02[AArch64] Allow MOVPRFX to be used with FMOVRichard Sandiford1-0/+5
2019-07-02[AArch64] Add missing C_MAX_ELEM flags for SVE conversionsRichard Sandiford1-0/+5
2019-07-02[AArch64] Fix bogus MOVPRFX warning for GPR form of CPYRichard Sandiford1-0/+5
2019-07-01[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson1-0/+15
2019-07-01x86: drop Vec_Imm4Jan Beulich1-0/+10
2019-07-01x86: limit ImmExt abuseJan Beulich1-0/+10
2019-07-01x86: optimize AND/OR with twice the same registerJan Beulich1-0/+6
2019-07-01x86-64: optimize certain commutative VEX-encoded insnsJan Beulich1-0/+32
2019-07-01x86: optimize EVEX packed integer logical instructionsJan Beulich1-0/+6
2019-07-01x86: add missing pseudo ops for VPCLMULQDQ ISA extensionJan Beulich1-0/+7
2019-07-01x86: drop bogus Disp8MemShift attributesJan Beulich1-0/+6
2019-07-01x86: remove ModRM.mod decoding layer from AVX512F VMOVS{S,D}Jan Beulich1-0/+19
2019-07-01x86: drop a few dead macrosJan Beulich1-0/+5
2019-06-27i386: Check vector length for scatter/gather prefetch instructionsH.J. Lu1-0/+24
2019-06-27x86: fold AVX scalar to/from int conversion insnsJan Beulich1-0/+9
2019-06-27x86: allow VEX et al encodings in 16-bit (protected) modeJan Beulich1-0/+12
2019-06-26RISC-V: Make objdump disassembly work right for binary files.Jim Wilson1-1/+7
2019-06-25x86: correct / adjust debug printingJan Beulich1-0/+8
2019-06-25x86: drop dqa_modeJan Beulich1-0/+11
2019-06-25x86: simplify OP_I64()Jan Beulich1-0/+5
2019-06-25x86: fix (dis)assembly of certain SSE2 insns in 16-bit modeJan Beulich1-0/+8
2019-06-25x86-64: also optimize ANDQ with immediate fitting in 7 bitsJan Beulich1-0/+5
2019-06-21i386: Break i386-dis-evex.h into small filesH.J. Lu1-0/+12
2019-06-19i386: Check vector length for EVEX broadcast instructionsH.J. Lu1-0/+23
2019-06-17i386: Check vector length for vshufXXX/vinsertXXX/vextractXXXH.J. Lu1-0/+26
2019-06-14Updated French translation for the opcodes subdirectory.Nick Clifton1-0/+4
2019-06-13opcodes/or1k: Regenerate opcodesStafford Horne1-0/+11
2019-06-12Add missing ChangeLog entriesPeter Bergner1-0/+4
2019-06-05i386: Check vector length for EVEX vextractfXX and vinsertfXXH.J. Lu1-0/+19
2019-06-04i386: Check for reserved VEX.vvvv and EVEX.vvvvH.J. Lu1-0/+13
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu1-0/+15
2019-06-04Add support for Intel ENQCMD[S] instructionsH.J. Lu1-0/+18
2019-06-04Remove an unnecessary set of parentheses in the arm-dis.c source file.Alan Hayward1-0/+4
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