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2017-03-13Sync libiberty sources with GCC.Nick Clifton2-2/+16
2017-03-13Rename R_AARCH64_TLSDESC_LD64_LO12_NC to R_AARCH64_TLSDESC_LD64_LO12 and R_AA...Nick Clifton2-2/+10
2017-03-10Add basic recognition of new EM_ ELF machine numbers.Nick Clifton2-18/+20
2017-03-08Properly dump NT_GNU_PROPERTY_TYPE_0H.J. Lu2-0/+18
2017-03-01Add support for displaying and merging GNU_BUILD_NOTEs.Nick Clifton2-0/+88
2017-02-28GDB: Add support for the new set/show disassembler-options commands.Peter Bergner2-4/+53
2017-02-28PowerPC addpcis fixAlan Modra3-2/+15
2017-02-24[AArch64] Additional SVE instructionsRichard Sandiford2-0/+13
2017-02-24[AArch64] Add a "compnum" featureRichard Sandiford2-1/+8
2017-02-24Add new counter-enable CSRsAndrew Waterman2-0/+11
2017-02-23S/390: Add support for new cpu architecture - arch12.Andreas Krebbel1-1/+4
2017-02-23opcodes,gas: associate SPARC ASIs with an architecture level.Sheldon Lobo1-1/+9
2017-02-15Add SFENCE.VMA instructionAndrew Waterman2-0/+9
2017-02-14PowerPC register expression checksAlan Modra2-70/+84
2017-02-06[ARC] Provide an interface to decode ARC instructions.Claudiu Zissulescu1-1/+23
2017-01-25Clarify that include/opcode/ files are part of GNU opcodesDimitar Dimitrov7-6/+15
2017-01-25Fix include/ChangeLog entry formatPedro Alves1-1/+1
2017-01-24[PATCH] Add NT_ARM_SVEAlan Hayward2-0/+6
2017-01-04[DWARF] Sync GCC dwarf.def change on AArch64Jiong Wang2-1/+18
2017-01-04[AArch64] Add separate feature flag for weaker release consistent load insnsSzabolcs Nagy2-1/+8
2017-01-03Add support for the Q extension to the RISCV ISA.Kito Cheng3-0/+108
2017-01-03Sync dwarf headers with master versions in gcc repository.Nick Clifton3-18/+213
2017-01-02Update year range in copyright notice of all files.Alan Modra300-299/+303
2017-01-02ChangeLog rotationAlan Modra2-829/+843
2017-01-01update copyright year range in GDB filesJoel Brobecker22-22/+22
2016-12-31PRU BFD supportDimitar Dimitrov5-1/+475
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki2-2/+13
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki2-5/+10
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki2-0/+8
2016-12-21Remove high bit set charactersAlan Modra3-9/+14
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki2-0/+12
2016-12-20Re-work RISC-V gas flags: now we just support -mabi and -marchAndrew Waterman2-2/+21
2016-12-20Rework RISC-V relocationsAndrew Waterman2-0/+13
2016-12-16Implement and document --gc-keep-exportedfincs2-0/+7
2016-12-14MIPS/opcodes: Also set disassembler's ASE flags from ELF structuresMaciej W. Rozycki2-1/+6
2016-12-13[Binutils][AARCH64]Remove Cn register for coprocessor CRn, CRm fieldRenlin Li2-3/+11
2016-12-09MIPS16: Remove unused `>' operand codeMaciej W. Rozycki2-2/+5
2016-12-07MIPS/include: opcode/mips.h: Correct INSN_CHIP_MASKMaciej W. Rozycki2-1/+5
2016-12-07MIPS/include: opcode/mips.h: Add a comment for ASE_DSPR3Maciej W. Rozycki2-0/+5
2016-12-05[ARM] Add ARMv8.3 command line option and feature flagSzabolcs Nagy2-0/+9
2016-11-29[ARC] Add checking for LP_COUNT reg usage, improve error reporting.Claudiu Zissulescu2-0/+10
2016-11-22gas,opcodes: fix hardware capabilities bumping in the sparc assembler.Jose E. Marchesi2-0/+9
2016-11-22PR20744, Incorrect PowerPC VLE relocsAlan Modra2-0/+22
2016-11-18libiberty: Add Rust symbol demangling.David Tolnay2-2/+39
2016-11-18Implement P0012R1, Make exception specifications part of the type system.Jason Merrill2-1/+8
2016-11-18[AArch64] Add ARMv8.3 FCMLA and FCADD instructionsSzabolcs Nagy2-0/+11
2016-11-18[AArch64] Add ARMv8.3 combined pointer authentication load instructionsSzabolcs Nagy2-0/+7
2016-11-11[AArch64] Add ARMv8.3 PACGA instructionSzabolcs Nagy2-0/+5
2016-11-11[AArch64] Add ARMv8.3 command line option and feature flagSzabolcs Nagy2-14/+13
2016-11-04Commit missing ChangeLog entry for Cortex-M33 supportThomas Preud'homme1-0/+6
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