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2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (dwarf_regnames_i386): Add AVX registers.
(dwarf_regnames_x86_64): Likewise.
gas/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
Document -msse2avx, .avx, .aes, .clmul and .fma.
* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
(vex_prefix): Likewise.
(sse2avx): Likewise.
(CPU_FLAGS_ARCH_MATCH): Likewise.
(CPU_FLAGS_64BIT_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(CPU_FLAGS_PERFECT_MATCH): Likewise.
(regymm): Likewise.
(vex_imm4): Likewise.
(fits_in_imm4): Likewise.
(build_vex_prefix): Likewise.
(VEX_check_operands): Likewise.
(bad_implicit_operand): Likewise.
(OPTION_MSSE2AVX): Likewise.
(T_YMMWORD): Likewise.
(_i386_insn): Add vex.
(cpu_arch): Add .avx, .aes, .clmul and .fma.
(cpu_flags_match): Changed to take a pointer to const template.
Enable encoding SSE instructions with VEX prefix for -msse2avx.
(match_mem_size): Also check ymmword.
(operand_type_match): Clear ymmword.
(md_begin): Allow '_' in mnemonic.
(type_names): Add OPERAND_TYPE_VEX_IMM4.
(process_immext): Update assert.
(md_assemble): Don't call process_immext if sse2avx and immext
are true. Call build_vex_prefix if vex is true.
(parse_insn): Updated for cpu_flags_match.
(swap_operands): Handle 5 operands.
(match_template): Handle 5 operands. Updated for cpu_flags_match.
Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
(check_byte_reg): Check regymm.
(process_operands): Duplicate the destination register for
-msse2avx if needed.
(build_modrm_byte): Updated for instructions with VEX encoding.
(output_insn): Output VEX prefix if needed.
(md_longopts): Add msse2avx.
(md_parse_option): Handle OPTION_MSSE2AVX.
(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
(intel_e09): Support YMMWORD.
(intel_e11): Likewise.
(intel_get_token): Likewise.
gas/testsuite/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
x86-64-avx-intel and x86-64-inval-avx.
* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/i386/aes.d: New.
* gas/i386/aes.s: Likewise.
* gas/i386/aes-intel.d: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/i386.exp: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-aes.d: Likewise.
* gas/i386/x86-64-aes.s: Likewise.
* gas/i386/x86-64-aes-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/rexw.s: Add AVX tests.
* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
* gas/cfi/cfi-i386.d: Updated.
* gas/cfi/cfi-x86_64.d: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/rexw.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
include/opcode/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
opcodes/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.
(OP_E_memory): Likewise.
(OP_VEX): Likewise.
(OP_EX_Vex): Likewise.
(OP_EX_VexW): Likewise.
(OP_XMM_Vex): Likewise.
(OP_XMM_VexW): Likewise.
(OP_REG_VexI4): Likewise.
(PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
(VZERO_Fixup): Likewise.
(VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(rex_original): Likewise.
(rex_ignored): Likewise.
(Mxmm): Likewise.
(XMM): Likewise.
(EXxmm): Likewise.
(EXxmmq): Likewise.
(EXymmq): Likewise.
(Vex): Likewise.
(Vex128): Likewise.
(Vex256): Likewise.
(VexI4): Likewise.
(EXdVex): Likewise.
(EXqVex): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(XMVex): Likewise.
(XMVexW): Likewise.
(XMVexI4): Likewise.
(PCLMUL): Likewise.
(VZERO): Likewise.
(VCMP): Likewise.
(VPERMIL2): Likewise.
(xmm_mode): Likewise.
(xmmq_mode): Likewise.
(ymmq_mode): Likewise.
(vex_mode): Likewise.
(vex128_mode): Likewise.
(vex256_mode): Likewise.
(USE_VEX_C4_TABLE): Likewise.
(USE_VEX_C5_TABLE): Likewise.
(USE_VEX_LEN_TABLE): Likewise.
(VEX_C4_TABLE): Likewise.
(VEX_C5_TABLE): Likewise.
(VEX_LEN_TABLE): Likewise.
(REG_VEX_XX): Likewise.
(MOD_VEX_XXX): Likewise.
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
(PREFIX_0F3A44): Likewise.
(PREFIX_0F3ADF): Likewise.
(PREFIX_VEX_XXX): Likewise.
(VEX_OF): Likewise.
(VEX_OF38): Likewise.
(VEX_OF3A): Likewise.
(VEX_LEN_XXX): Likewise.
(vex): Likewise.
(need_vex): Likewise.
(need_vex_reg): Likewise.
(vex_i4_done): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(OP_REG_VexI4): Likewise.
(vex_cmp_op): Likewise.
(pclmul_op): Likewise.
(vpermil2_op): Likewise.
(m_mode): Updated.
(es_reg): Likewise.
(PREFIX_0F38F0): Likewise.
(PREFIX_0F3A60): Likewise.
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
and PREFIX_VEX_XXX entries.
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
PREFIX_0F3ADF.
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
Add MOD_VEX_XXX entries.
(ckprefix): Initialize rex_original and rex_ignored. Store the
REX byte in rex_original.
(get_valid_dis386): Handle the implicit prefix in VEX prefix
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
calling get_valid_dis386. Use rex_original and rex_ignored when
printing out REX.
(putop): Handle "XY".
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
ymmq_mode.
(OP_E_extended): Updated to use OP_E_register and
OP_E_memory.
(OP_XMM): Handle VEX.
(OP_EX): Likewise.
(XMM_Fixup): Likewise.
(CMP_Fixup): Use ARRAY_SIZE.
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
(operand_type_init): Add OPERAND_TYPE_REGYMM and
OPERAND_TYPE_VEX_IMM4.
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
VexImmExt and SSE2AVX.
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
* i386-opc.h (CpuAVX): New.
(CpuAES): Likewise.
(CpuCLMUL): Likewise.
(CpuFMA): Likewise.
(Vex): Likewise.
(Vex256): Likewise.
(VexNDS): Likewise.
(VexNDD): Likewise.
(VexW0): Likewise.
(VexW1): Likewise.
(Vex0F): Likewise.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(Vex3Sources): Likewise.
(VexImmExt): Likewise.
(SSE2AVX): Likewise.
(RegYMM): Likewise.
(Ymmword): Likewise.
(Vex_Imm4): Likewise.
(Implicit1stXmm0): Likewise.
(CpuXsave): Updated.
(CpuLM): Likewise.
(ByteOkIntel): Likewise.
(OldGcc): Likewise.
(Control): Likewise.
(Unspecified): Likewise.
(OTMax): Likewise.
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
vex3sources, veximmext and sse2avx.
(i386_operand_type): Add regymm, ymmword and vex_imm4.
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
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2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
* config/tc-avr.c (mcu_types): Add attiny167.
* doc/c-avr.texi: Likewise.
/include:
2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
* opcode/avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
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* opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z10 added.
(s390_cond_extensions): Reduced extensions to the compare related.
(main): z10 cpu type option added.
(expandConditionalJump): Renamed to ...
(insertExpandedMnemonic): ... this.
* opcodes/s390-opc.c: Re-group the operand format makros.
(INSTR_RIE_RRPU, INSTR_RIE_RRP0, INSTR_RIE_RUPI,
INSTR_RIE_R0PI, INSTR_RIE_RUPU, INSTR_RIE_R0PU, INSTR_RIE_R0IU,
INSTR_RIE_R0I0, INSTR_RIE_R0UU, INSTR_RIE_R0U0,
INSTR_RIE_RRUUU, INSTR_RIS_RURDI, INSTR_RIS_R0RDI, INSTR_RIS_RURDU,
INSTR_RIS_R0RDU, INSTR_RRF_U0RR, INSTR_RRF_00RR, INSTR_RRS_RRRDU,
INSTR_RRS_RRRD0, INSTR_RXY_URRD, INSTR_SIY_IRD, INSTR_SIL_RDI,
INSTR_SIL_RDU): New instruction formats added.
(MASK_RIE_RRPU, MASK_RIE_RRP0, MASK_RIE_RUPI, MASK_RIE_R0PI,
MASK_RIE_RUPU, MASK_RIE_R0PU, MASK_RIE_R0IU, MASK_RIE_R0I0,
MASK_RIE_R0UU, MASK_RIE_R0U0, MASK_RIE_RRUUU, MASK_RIS_RURDI,
MASK_RIS_R0RDI, MASK_RIS_RURDU, MASK_RIS_R0RDU, MASK_RRF_U0RR,
MASK_RRF_00RR, MASK_RRS_RRRDU, MASK_RRS_RRRD0, MASK_RXY_URRD,
MASK_SIY_IRD, MASK_SIL_RDI, MASK_SIL_RDU): New instruction format
masks added.
(s390_opformats): New formats added "ris", "rrs", "sil".
* opcodes/s390-opc.txt: Add the conditional jumps with the
extensions removed from automatic expansion in s390-mkopc.c manually.
(asi - trtre): Add new System z10 EC instructions.
* include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z10 added.
2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
* config/tc-s390.c (md_parse_option): z10 option added.
2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com>
* gas/s390/zarch-z10.d: New file.
* gas/s390/zarch-z10.s: New file.
* gas/s390/s390.exp: Run the z10 testcases.
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bfd/
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle new
Tag_VFP_arch values.
binutils/
* readelf.c (arm_attr_tag_VFP_arch): Add "VFPv3-D16".
gas/
* config/tc-arm.c (fpu_vfp_ext_d32): New vairable.
(parse_vfp_reg_list, encode_arm_vfp_reg): Use it.
(arm_option_cpu_value): Add vfpv3-d16, vfpv2 and vfpv3.
(aeabi_set_public_attributes): Handle Tag_VFP_arch=VFPV3-D16.
* doc/c-arm.texi: Document new ARM FPU variants.
gas/testsuite/
* gas/arm/vfpv3-d16-bad.d: New test.
* gas/arm/vfpv3-d16-bad.l: New test.
include/opcode/
* arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
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gas/
* config/tc-arm.c (arm_ext_barrier, arm_ext_msr): New.
(arm_ext_v7m): Rename...
(arm_ext_m): ... to this. Include v6-M.
(do_t_add_sub): Allow narrow low-reg non flag setting adds.
(do_t_mrs, do_t_msr, aeabi_set_public_attributes): Use arm_ext_m.
(md_assemble): Allow wide msr instructions.
(insns): Add classifications for v6-m instructions.
(arm_cpu_option_table): Add cortex-m1.
(arm_arch_option_table): Add armv6-m.
(cpu_arch): Add ARM_ARCH_V6M. Fix numbering of other v6 variants.
gas/testsuite/
* gas/arm/archv6m.d: New test.
* gas/arm/archv6m.s: New test.
* gas/arm/t16-bad.s: Test low register non flag setting add.
* gas/arm/t16-bad.l: Update expected output.
include/opcode/
* arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
(ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
(ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
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* h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
with a 32-bit displacement but without the top bit of the 4th byte
set.
* gas/h8300/pr3134.s: New test.
* gas/h8300/pr3134.d: Expected disassembly
* gas/h8300/h8300.exp: Run the new test.
* gas/h8300/h8300-coff.exp: Fix test for COFF based ports to
accept h8300-rtemscoff not just h8300-rtems.
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* cr16-opc.c (cr16_num_optab): Defined
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* avr.h (AVR_ISA_2xxe): Define.
* config/tc-avr.c (mcu_types): Change the ISA tyoe of the attiny26
to AVR_ISA_2xxe.
(avr_operand): Disallow post-increment addressing in the lpm
instruction for the attiny26.
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(INSN_CHIP_MASK): New macro.
(INSN_OCTEON): New macro.
(CPU_OCTEON): New macro.
(OPCODE_IS_MEMBER): Handle Octeon instructions.
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2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
* config/tc-avr.c (mcu_types): Change opcode set for at86rf401.
/include:
2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
* opcode/avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
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2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
* config/tc-avr.c (mcu_types): Change opcode set for avr3,
at90usb82, at90usb162.
* doc/c-avr.texi: Change architecture grouping for at90usb82,
at90usb162.
These changes support the new avr35 architecture group in gcc.
/include:
2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
* opcode/avr.h (AVR_ISA_USB162): Add new opcode set.
(AVR_ISA_AVR3): Likewise.
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* archures.c (bfd_mach_mips_loongson_2e): New.
(bfd_mach_mips_loongson_2f): New.
* bfd-in2.h (bfd_mach_mips_loongson_2e): New.
(bfd_mach_mips_loongson_2f): New.
* cpu-mips.c: Add I_loongson_2e and I_loongson_2f to
anonymous enum.
(arch_info_struct): Add Loongson-2E and Loongson-2F entries.
* elfxx-mips.c (_bfd_elf_mips_mach): Handle Loongson-2E
and Loongson-2F flags.
(mips_set_isa_flags): Likewise.
(mips_mach_extensions): Add Loongson-2E and Loongson-2F
entries.
binutils/
* readelf.c (get_machine_flags): Handle Loongson-2E and -2F
flags.
gas/
* config/tc-mips.c (mips_cpu_info_table): Add loongson2e
and loongson2f entries.
* doc/c-mips.texi: Document -march=loongson{2e,2f} options.
gas/testsuite/
* gas/mips/mips.exp: Add loongson-2e and -2f tests.
* gas/mips/loongson-2e.d: New.
* gas/mips/loongson-2e.s: New.
* gas/mips/loongson-2f.d: New.
* gas/mips/loongson-2f.s: New.
include/elf/
* mips.h (E_MIPS_MACH_LS2E): New.
(E_MIPS_MACH_LS2F): New.
include/opcode/
* mips.h (INSN_LOONGSON_2E): New.
(INSN_LOONGSON_2F): New.
(CPU_LOONGSON_2E): New.
(CPU_LOONGSON_2F): New.
(OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
opcodes/
* mips-dis.c (mips_arch_choices): Add Loongson-2E and -2F
entries.
* mips-opc.c (IL2E): New.
(IL2F): New.
(mips_builtin_opcodes): Add Loongson-2E and -2F instructions.
Allow movz and movn for Loongson-2E and -2F. Add movnz entry.
Move coprocessor encodings to the end of the table. Allow
certain MIPS V .ps instructions on the Loongson-2E and -2F.
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* mips.h (INSN_ISA*): Redefine certain values as an
enumeration. Update comments.
(mips_isa_table): New.
(ISA_MIPS*): Redefine to match enumeration.
(OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
values.
opcodes/
* mips-opc.c (I3_32, I3_33, I4_32, I4_33, I5_33): New.
(mips_builtin_opcodes): Use these new I* values.
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* doc/binutils.texi (objdump): Document -Mppcps.
gas/
* config/tc-ppc.c (parse_cpu): Handle "750cl".
(pre_defined_registers): Add "gqr0" to "gqr7", "gqr.0" to "gqr.7".
(md_show_usage): Document -m750cl.
(md_assemble): Handle two delimiters in succession (eg. `),').
* doc/c-ppc.texi (PowerPC-Opts): Document -m750cl.
* testsuite/gas/ppc/ppc.exp: Run ppc70ps dump tests.
* testsuite/gas/ppc/ppc750ps.s: New file.
* testsuite/gas/ppc/ppc750ps.d: Likewise.
include/opcode/
* ppc.h (PPC_OPCODE_PPCPS): New.
opcodes/
* ppc-opc.c (PSW, PSWM, PSQ, PSQM, PSD, MTMSRD_L): New.
(XOPS, XOPS_MASK, XW, XW_MASK): Likewise.
(PPCPS): Likewise.
(powerpc_opcodes): Add all pair singles instructions.
* ppc-dis.c (powerpc_dialect): Handle "ppcps".
(print_ppc_disassembler_options): Document -Mppcps.
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* gas/m68k/mcf-coproc.d: New.
* gas/m68k/mcf-coproc.s: New.
* gas/m68k/all.exp: Add it.
gas/
* config/tc-m68k.c (m68k_ip): Add j & K operand types.
(install_operand): Add E encoding.
(md_begin): Check and skip initial '.' arg character.
(get_num): Add 0..511 case.
include/
* opcode/m68k.h: Document j K & E.
opcodes/
* m68k-dis.c (fetch_arg): Add E. Replace length switch with
direct masking.
(print_ins_arg): Add j & K operand types.
(match_insn_m68k): Check and skip initial '.' arg character.
(m68k_scan_mask): Likewise.
* m68k-opc.c (m68k_opcodes): Add coprocessor instructions.
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PR 4448
* config/tc-ppc.c (ppc_insert_operand): Don't increase min for
PPC_OPERAND_PLUS1.
include/opcode/
* ppc.h (PPC_OPERAND_PLUS1): Update comment.
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* gas/m68k/br-isaa.s: New.
* gas/m68k/br-isaa.d: New.
* gas/m68k/br-isab.s: New.
* gas/m68k/br-isab.d: New.
* gas/m68k/br-isac.s: New.
* gas/m68k/br-isac.d: New.
* gas/m68k/all.exp: Adjust.
gas/
* config/tc-m68k.c (mcf54455_ctrl): New.
(HAVE_LONG_DISP, HAVE_LONG_CALL, HAVE_LONG_COND): New.
(m68k_archs): Add isac.
(m68k_cpus): Add 54455 family.
(m68k_ip): Split Bg into Bb, Bs, Bg.
(m68k_elf_final_processing): Add ISA_C.
* doc/c-m68k.texi (M680x0 Options): Add isac.
include/opcode/
* m68k.h (mcfisa_c): New.
(mcfusp, mcf_mask): Adjust.
bfd/
* archures.c (bfd_mach_mcf_isa_c, bfd_mach_mcf_isa_c_mac,
bfd_mach_mcf_isa_c_emac): New.
* elf32-m68k.c (ISAC_PLT_ENTRY_SIZE, elf_isac_plt0_entry,
elf_isac_plt_entry, elf_isac_plt_info): New.
(elf32_m68k_object_p): Add ISA_C.
(elf32_m68k_print_private_bfd_data): Print ISA_C.
(elf32_m68k_get_plt_info): Detect ISA_C.
* cpu-m68k.c (arch_info): Add ISAC.
(m68k_arch_features): Likewise,
(bfd_m68k_compatible): ISAs B & C are not compatible.
opcodes/
* m68k-opc.c: Mark mcfisa_c instructions.
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* ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
(num_powerpc_operands): Declare.
(PPC_OPERAND_SIGNED et al): Redefine as hex.
(PPC_OPERAND_PLUS1): Define.
opcodes/
* ppc-dis.c (print_insn_powerpc): Adjust for struct powerpc_operand
change.
* ppc-opc.c (powerpc_operands): Replace bit count with bit mask
in all entries. Add PPC_OPERAND_SIGNED to DE entry. Remove
references to following deleted functions.
(insert_bd, extract_bd, insert_dq, extract_dq): Delete.
(insert_ds, extract_ds, insert_de, extract_de): Delete.
(insert_des, extract_des, insert_li, extract_li): Delete.
(insert_nb, insert_rsq, insert_rtq, insert_ev2, extract_ev2): Delete.
(insert_ev4, extract_ev4, insert_ev8, extract_ev8): Delete.
(num_powerpc_operands): New constant.
(XSPRG_MASK): Remove entire SPRG field.
(powerpc_opcodes <bcctre, bcctrel>): Use XLBB_MASK not XLYBB_MASK.
gas/
* messages.c (as_internal_value_out_of_range): Extend to report
errors for values with invalid low bits set.
* config/tc-ppc.c (ppc_setup_opcodes): Check powerpc_operands bitm
fields. Check that operands and opcode fields are disjoint.
(ppc_insert_operand): Check operands using mask rather than bit
count. Check low bits too. Handle PPC_OPERAND_PLUS1. Adjust
insertion code.
(md_apply_fix): Adjust for struct powerpc_operand change.
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2003-03-21 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c: Replace REX_MODE64, REX_EXTX, REX_EXTY
and REX_EXTZ with REX_W, REX_R, REX_X and REX_B respectively.
include/opcode/
2003-03-21 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (REX_MODE64): Renamed to ...
(REX_W): This.
(REX_EXTX): Renamed to ...
(REX_R): This.
(REX_EXTY): Renamed to ...
(REX_X): This.
(REX_EXTZ): Renamed to ...
(REX_B): This.
opcodes/
2003-03-21 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (REX_MODE64): Remove definition.
(REX_EXTX): Likewise.
(REX_EXTY): Likewise.
(REX_EXTZ): Likewise.
(USED_REX): Use REX_OPCODE instead of 0x40.
Replace REX_MODE64, REX_EXTX, REX_EXTY and REX_EXTZ with REX_W,
REX_R, REX_X and REX_B respectively.
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2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
* Makefile.am: Run "make dep-am".
* Makefile.in: Regenerated.
* config/tc-i386.c: Include "opcodes/i386-opc.h" instead of
"opcode/i386.h".
(md_begin): Check reg_name != NULL for the last entry in
i386_regtab.
* config/tc-i386.h: Move many entries to opcode/i386.h and
opcodes/i386-opc.h.
* configure.in (need_opcodes): Set true for i386.
* configure: Regenerated.
include/opcode/
2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
* i386.h: Add entries from config/tc-i386.h and move tables
to opcodes/i386-opc.h.
opcodes/
2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
* Makefile.am (CFILES): Add i386-opc.c.
(ALL_MACHINES): Add i386-opc.lo.
Run "make dep-am".
* Makefile.in: Regenerated.
* configure.in: Add i386-opc.lo for bfd_i386_arch.
* configure: Regenerated.
* i386-dis.c: Include "opcode/i386.h".
(MAXLEN): Renamed to MAX_MNEM_SIZE. Remove definition.
(FWAIT_OPCODE): Remove definition.
(UNIXWARE_COMPAT): Renamed to SYSV386_COMPAT. Remove definition.
(MAX_OPERANDS): Remove definition.
* i386-opc.c: New file.
* i386-opc.h: Likewise.
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* i386.h (FloatDR): Removed.
(i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
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* opcodes/s390-opc.c (INSTR_RRE_FR, INSTR_RRF_F0FF2, INSTR_RRF_F0FR,
INSTR_RRF_UUFF, INSTR_RRF_0UFF, INSTR_RRF_FFFU, INSTR_RRR_F0FF): New
instruction formats added.
(MASK_RRE_FR, MASK_RRF_F0FF2, MASK_RRF_F0FR, MASK_RRF_UUFF,
MASK_RRF_0UFF, MASK_RRF_FFFU, MASK_RRR_F0FF): New instruction format
masks added.
* opcodes/s390-opc.txt (lpdfr - tgxt): Decimal floating point
instructions added.
* opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added.
(main): z9-ec cpu type option added.
* include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added.
2007-03-06 Andreas Krebbel <krebbel1@de.ibm.com>
* config/tc-s390.c (md_parse_option): z9-ec option added.
2007-03-06 Andreas Krebbel <krebbel1@de.ibm.com>
* gas/s390/zarch-z9-ec.d: New file.
* gas/s390/zarch-z9-ec.s: New file.
* gas/s390/s390.exp: Run the z9-ec testcases.
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* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
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* config/tc-i386.h (Seg2ShortForm, Seg3ShortForm): Delete.
* config/tc-i386.c: Wrap overly long lines, whitespace fixes.
(process_operands): Move old Seg2ShortForm and Seg3ShortForm
code, and test for these insns using a combination of
opcode_modifier and operand_types.
include/opcode/
* i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
and Seg3ShortFrom with Shortform.
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2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
PR gas/4027
* gas/i386/opcode.s: Add more tests for "test".
* i386/opcode-intel.d: Updated.
* gas/i386/opcode-suffix.d: Likewise.
* gas/i386/opcode.d: Likewise.
include/opcode/
2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
PR gas/4027
* i386.h (i386_optab): Put the real "test" before the pseudo
one.
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* archures.c (bfd_mach_cpu32_fido): Rename to bfd_mach_fido.
* bfd-in2.h: Regenerate.
* cpu-m68k.c (arch_info_struct): Use bfd_mach_fido instead of
bfd_mach_cpu32_fido.
(m68k_arch_features): Use fido_a instead of cpu32.
(bfd_m68k_compatible): Reject the combination of Fido and
ColdFire. Accept the combination of CPU32 and Fido with a
warning.
* elf32-m68k.c (elf32_m68k_object_p,
elf32_m68k_merge_private_bfd_data,
elf32_m68k_print_private_bfd_data): Treat Fido as an
architecture by itself.
binutils/
* readelf.c (get_machine_flags): Treat Fido as an architecture
by itself.
gas/
* config/tc-m68k.c (m68k_archs, m68k_cpus): Treat Fido as an
architecture by itself.
(m68k_ip): Don't issue a warning for tbl instructions on fido.
(m68k_elf_final_processing): Treat Fido as an architecture by
itself.
include/elf/
* m68k.h (EF_M68K_FIDO): New.
(EF_M68K_ARCH_MASK): OR EF_M68K_FIDO.
(EF_M68K_CPU32_FIDO_A, EF_M68K_CPU32_MASK): Remove.
include/opcode/
* m68k.h (m68010up): OR fido_a.
opcodes/
* m68k-opc.c (m68k_opcodes): Replace cpu32 with
cpu32 | fido_a except on tbl instructions.
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* archures.c (bfd_mach_cpu32_fido): New.
(bfd_mach_mcf_isa_a_nodiv, bfd_mach_mcf_isa_a,
bfd_mach_mcf_isa_a_mac, bfd_mach_mcf_isa_a_emac,
bfd_mach_mcf_isa_aplus, bfd_mach_mcf_isa_aplus_mac,
bfd_mach_mcf_isa_aplus_emac, bfd_mach_mcf_isa_b_nousp,
bfd_mach_mcf_isa_b_nousp_mac, bfd_mach_mcf_isa_b_nousp_emac,
bfd_mach_mcf_isa_b, bfd_mach_mcf_isa_b_mac,
bfd_mach_mcf_isa_b_emac, bfd_mach_mcf_isa_b_float,
bfd_mach_mcf_isa_b_float_mac, bfd_mach_mcf_isa_b_float_emac):
Increment the defined values.
* bfd-in2.h: Regenerate.
* cpu-m68k.c (arch_info_struct): Add en entry for
bfd_mach_cpu32_fido.
* elf32-m68k.c (elf32_m68k_object_p): Handle
EF_M68K_CPU32_FIDO_A.
(elf32_m68k_merge_private_bfd_data): Use EF_M68K_CPU32_MASK.
(elf32_m68k_print_private_bfd_data): Handle
EF_M68K_CPU32_FIDO_A.
binutils/
* readelf.c (get_machine_flags): Handle EF_M68K_CPU32_FIDO_A.
gas/
* config/tc-m68k.c (cpu_of_arch): Add fido.
(m68k_archs, m68k_cpu): Add entries for fido.
(m68k_elf_final_processing): Handle EF_M68K_CPU32_FIDO_A.
include/elf/
* m68k.h (EF_M68K_CPU32_FIDO_A, EF_M68K_CPU32_MASK): New.
include/opcode/
* m68k.h (fido_a): New.
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mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
values.
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2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.h (CpuPNI): Removed.
(CpuUnknownFlags): Replace CpuPNI with CpuSSE3.
* config/tc-i386.c (md_assemble): Likewise.
include/opcode/
2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
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(my_get_expression): Const operand of some instructions can not be symbol in assembly.
(get_insn_class_from_type): Handle instruction type Insn_internal.
(do_macro_ldst_label): Modify inst.type.
(Insn_PIC): Delete.
* score-inst.h (enum score_insn_type): Add Insn_internal.
* tc-score.c (data_op2): The immediate value in lw is 15 bit signed.
* score-dis.c (print_insn): Correct the error code to print correct PCE instruction disassembly.
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2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.h (CpuMNI): Renamed to ...
(CpuSSSE3): This.
(CpuUnknownFlags): Updated.
(processor_type): Replace PROCESSOR_YONAH with PROCESSOR_CORE
and PROCESSOR_MEROM with PROCESSOR_CORE2.
* config/tc-i386.c: Updated.
* doc/c-i386.texi: Likewise.
* config/tc-i386.c (cpu_arch): Add ".ssse3", "core" and "core2".
include/opcode/
2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
* i386.h: Replace CpuMNI with CpuSSSE3.
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2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* archures.c: Add definition for bfd_mach_arm_iWMMXt2.
* cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2.
(arch_info_struct, bfd_arm_update_notes): Likewise.
(architectures): Likewise.
(bfd_arm_merge_machines): Check for iWMMXt2.
* bfd-in2.h: Rebuild.
gas/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* config/tc-arm.c (arm_cext_iwmmxt2): New.
(enum operand_parse_code): New code OP_RIWR_I32z.
(parse_operands): Handle OP_RIWR_I32z.
(do_iwmmxt_wmerge): New function.
(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
a register.
(do_iwmmxt_wrwrwr_or_imm5): New function.
(insns): Mark instructions as RIWR_I32z as appropriate.
Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
(md_begin): Handle IWMMXT2.
(arm_cpus): Add iwmmxt2.
(arm_extensions): Likewise.
(arm_archs): Likewise.
gas/testsuite/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* gas/arm/iwmmxt2.s: New file.
* gas/arm/iwmmxt2.d: New file.
include/opcode/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
opcodes/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
only be used with the default multiply-add operation, so if N is
set, don't bother printing X. Add new iwmmxt instructions.
(IWMMXT_INSN_COUNT): Update.
(iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
with a 'c' suffix.
(print_insn_coprocessor): Check for iWMMXt2. Handle format
specifiers 'r', 'i'.
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* i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
movdq2q and movq2dq.
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2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run nops and x86-64-nops.
* gas/i386/nops.d: New file.
* gas/i386/nops.s: Likewise.
* gas/i386/x86-64-nops.d: Likewise.
* gas/i386/x86-64-nops.s: Likewise.
include/opcode/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Add "nop" with memory reference.
opcodes/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
(twobyte_has_modrm): Set 1 for 0x1f.
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2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_suffix): Don't add rex64 for
"xchg %rax,%rax".
gas/testsuite/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/opcode.s: Add "xchg %ax,%ax".
* gas/i386/opcode.d: Updated.
* gas/i386/x86-64-opcode.s: Add xchg %ax,%ax, xchg %eax,%eax,
xchg %rax,%rax, rex64 xchg %rax,%rax and xchg %rax,%r8.
* gas/i386/x86-64-opcode.d: Updated.
include/opcode/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Update comment for 64bit NOP.
opcodes/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (NOP_Fixup): Removed.
(NOP_Fixup1): New.
(NOP_Fixup2): Likewise.
(dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
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* ppc.h (PPC_OPCODE_POWER6): Define.
Adjust whitespace.
gas/
* config/tc-ppc.c (parse_cpu): Handle "-mpower6".
(md_show_usage): Document it.
(ppc_setup_opcodes): Test power6 opcode flag bits.
* doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6".
opcodes/
* ppc-dis.c (powerpc_dialect): Handle power6 option.
(print_ppc_disassembler_options): Mention power6.
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* config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro.
(CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete.
(macro_build): Update comment.
(mips_ip): Allow DSP64 instructions for MIPS64R2.
(mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and
CPU_HAS_MDMX.
(mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and
MIPS_CPU_ASE_MDMX flags for sb1.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips64-dsp.s, gas/mips/mips64-dsp.d: New DSP64 tests.
* gas/mips/mips.exp: Run DSP64 tests.
[ opcodes/ChangeLog ]
* mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
* mips-opc.c: Add DSP64 instructions.
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