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2025-12-09LoongArch: Add support for the ud macro instructionLulu Cai1-0/+3
In the "ud ui5" macro, the value of ui5 must be in the range 0–31. It expands to "amswap.w $rd, $r1, $rj", where ui5 specifies the register number for $rd in the amswap.w instruction, and $rd == $rj. The test case have been adjusted to no longer report errors for illegal operands of the amswap.w instruction. gas/ * config/tc-loongarch.c (check_this_insn_before_appending): No longer check amswap.w. * testsuite/gas/loongarch/illegal-operand.l: Update. * testsuite/gas/loongarch/illegal-operand.s: Update. * testsuite/gas/loongarch/macro_ud.d: New test. * testsuite/gas/loongarch/macro_ud.s: New test. include/ * opcode/loongarch.h: Add new macro for amswap.w. opcodes/ * loongarch-opc.c: Add macro for ud.
2025-12-04aarch64: Improve comment for aarch64_opnd_info.sysreg.flagsAlice Carlotti1-1/+3
This field is used differently during assembly and disassembly. It would be nice if we could make this more consistent, but for now just extend the comment to explain what is going on.
2025-11-21RISC-V: Fixed opcodes for some bitmanip instructionstimurgol0071-0/+44
Currently some of the instructions in bitmanip extensions can not be obtained using DECLARE_INSN macros. I generated them using riscv-opcodes and added to other opcodes. Approved-By: Nelson Chu <nelson@rivosinc.com>
2025-10-10aarch64: Add support for FEAT_SSVE_BITPERMAlice Carlotti1-0/+4
2025-10-10aarch64: Add support for FEAT_SSVE_FEXPAAlice Carlotti1-0/+4
2025-10-10aarch64: Add support for FEAT_SME_MOP4Alice Carlotti1-2/+8
2025-10-10aarch64: Add support for FEAT_SME_TMOPAlice Carlotti1-0/+3
2025-10-10aarch64: Remove incorrect disassembly constraintAlice Carlotti1-1/+0
A check in print_insn_aarch64_word asserted that part of the encoding space couldn't contain any valid encodings, and then returned ERR_NYI ("Not Yet Implemented", perhaps?) for these values. However, some of the new FEAT_MOP4 instructions will trigger the assert. The check seems to be outdated, and is clearly no longer valid, so it can just be deleted. Additionally, there are no other assignments of ERR_NYI, so delete all remaining references to this error type.
2025-10-08aarch64, gas: Relax Armv9.6-A mandatory feature setAndre Vieira1-3/+1
Remove FPRCVT and SVE2p2 from the set of mandatory features for Armv9.6-A.
2025-10-06gas: aarch64: Add instructions for GICv5Saurabh Jha1-0/+6
Add new instructions from the Generic Interrupt Controller, GICv5, extension. These instructions are aliases to system instructions and are the following: * gic <operation>, <reg> * gicr <reg>, <operation> * gsb <operation>
2025-10-06gas: aarch64: Add flag for GICv5Saurabh Jha1-0/+2
Generic Interrupt Controller v5, GICv5, adds new system registers and system instructions. These are enabled with the +gcie flag, where gcie stands for GICv5 (Generic Interrupt Controller) CPU Interrupt Extension.
2025-09-23aarch64: Reorder feature bitsAlice Carlotti1-36/+23
Group the architecture version bits at the start of the enum, and add a comment explaining the purpose of AARCH64_FEATURE_V8A.
2025-09-23aarch64: Remove unused feature bitsAlice Carlotti1-69/+0
Many feature bits were unnecessarily added for features with no command line flags, and effectively acted as aliases of the architecture version bit they were linked to. The system register regating patch removed all uses of these feature bits, so we can just remove them.
2025-09-23aarch64: Remove F_ARCHEXT flagAlice Carlotti1-1/+1
The flag is unnecessary, because we can just unconditionally check the features field every time. Having the information duplicated in two separate fields makes it harder to maintain, particularly in the context of the upcoming regating patch. The reg_flags parameter of aarch64_sys_ins_reg_supported_p is now unused, so remove that as well.
2025-07-12aarch64: Add support for --march=armv9.6-aAlice Carlotti1-0/+10
2025-07-12aarch64: Refactor exclusion of reg names in immediatesAlice Carlotti1-1/+18
When parsing immediate values, register names should not be misinterpreted as symbols. However, for backwards compatibility we need to permit some newer register names within older instructions. The current mechanism for doing so depends on the list of explicit architecture requirements for the instructions, which is fragile and easy to forget, and grows increasingly messy as more architecture features are added. This patch add explicit flags to each opcode to indicate which set of register names is disallowed in each instance. These flags are mandatory for all opcodes with immediate operands, which ensures that the choice of disallowed names will always be deliberate and explicit. This patch should have no functional change.
2025-07-11aarch64: Support for FEAT_SVE_AES2Ezra Sitorus1-0/+9
FEAT_SVE_AES2 implements the SVE multi-vector Advanced Encryption Standard and 128-bit destination element polynomial multiply long instructions, when the PE is not in Streaming SVE mode.
2025-07-11aarch64: Support for FEAT_LSUIEzra Sitorus1-0/+2
FEAT_LSUI introduces unprivileged variants of load and store instructions so that clearing PSTATE.PAN is never required in privileged software.
2025-07-11aarch64: Support for FEAT_PCDPHINTEzra Sitorus1-0/+3
FEAT_PCDPHINT - Producer-consumer data placement hints - is an optional ISA extension that provides hint instructions to indicate: - a store in the current execution thread is generating data at a specific location, which a thread of execution on one or more other observers is waiting on. - the thread of execution on the current PE will read a location that may not yet have been written with the value to be consumed. This extension introduces: - STSHH, a hint instruction, with operands (policies) keep and strm - PRFM *IR*, a new prefetch memory operand.
2025-07-10RISC-V: Clarify the imply rule of cNelson Chu1-4/+4
This also fix the imply result for .option rvc. Imply zcf when c and f and rv32 Imply zcd when c and d Imply zca when c Changed INSN_CLASS_C to INSN_CLASS_ZCA Changed INSN_CLASS_F_AND_C to INSN_CLASS_ZCF Changed INSN_CLASS_D_AND_C to INSN_CLASS_ZCD Changed INSN_CLASS_ZIHINTNTL_AND_C to INSN_CLASS_ZIHINTNTL_AND_ZCA
2025-07-09gas d30v_insn plus other non-const pointersAlan Modra1-2/+2
d30v has a bunch of casts that are only needed due to various types missing a const. Fix that.
2025-07-08aarch64: Add support for FEAT_SVE2p2 and FEAT_SME2p2Alice Carlotti1-1/+12
2025-06-25aarch64: Add supports for FEAT_PoPS feature and DC instructions.Srinath Parvathaneni1-0/+2
This patch add support for FEAT_PoPS feature which can be enabled through +pops command line flag. This patch also adds support for following DC instructions and the spec can be found here [1]. 1. "dc cigdvaps" enabled on passing +memtag+pops command line flags. 2. "dc civaps" enabled on passing +pops command line flag. [1]: https://developer.arm.com/documentation/ddi0601/2025-03/AArch64-Instructions?lang=en
2025-06-24RISC-V: Support for unlabeled landing pad PLT generationKito Cheng1-0/+1
This patch adds support for generating unlabeled landing pad PLT entries for the RISC-V architecture. Unlabeled landing pad will place a LPAD instruction at the PLT entry and PLT header, also PLT header will have few changes due to the offset is different from the original one. Ref: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/417
2025-06-19aarch64: Support for FEAT_LSFEEzra Sitorus1-2/+7
FEAT_LSFE - Large System Float Extension - implements A64 base atomic floating-point in-memory instructions.
2025-06-19aarch64: Support for FEAT_SVE_F16F32MM, FEAT_F8F16M, FEAT_F8F32MMEzra Sitorus1-0/+6
FEAT_SVE_F16F32MM introduces the SVE half-precision floating-point matrix multiply-accumulate to single-precision instruction. FEAT_F8F32MM introduces the Advanced SIMD 8-bit floating-point matrix multiply-accumulate to single-precision instruction. FEAT_F8F16MM introduces the Advanced SIMD 8-bit floating-point matrix multiply-accumulate to half-precision instruction.
2025-06-19aarch64: Support for FEAT_CMPBREzra Sitorus1-0/+5
FEAT_CMPBR - Compare and branch instructions. This patch adds these instructions: - CB<CC> (register) - CB<CC> (immediate) - CBH<CC> - CBB<CC> where CC is one of the following: - EQ - NE - GT - GE - LT - LE - HI - HS - LO - LS
2025-06-19aarch64: Add occmo flag for FEAT_OCCMOEzra Sitorus1-0/+2
FEAT_OCCMO support was introduced, but the feature flags were missing. This patch adds these flags, as well as splitting up the tests to test occmo vs occmo+memtag operands.
2025-06-19aarch64: Support for FEAT_SVE_BFSCALEEzra Sitorus1-0/+5
FEAT_SVE_BFSCALE introduces the SVE BFSCALE instruction, when the PE is not in Streaming SVE mode. If FEAT_SME2 is implemented, FEAT_SVE_BFSCALE also introduces SME multi-vector Z-targeting BFloat16 scaling instructions, BFSCALE and BFMUL.
2025-06-12aarch64: Add support for FEAT_FPRCVTRichard Ball1-0/+4
FEAT_FPRCVT introduces new versions of previous instructions. The instructions are used to convert between floating points and Integers. These new versions take as operands SIMD&FP registers for both the source and destination register. FEAT_FPRCVT also enables the use of some existing AdvSIMD instructions in streaming mode. However, no changes are needed in gas to support this.
2025-06-11aarch64: Add definitions for missing architecture bitsYury Khrustalev1-4/+16
Complete macros for feature bits for v9.1-A, v9.2-A, v9.3-A, and v9.4-A.
2025-06-11kvx gcc-4.5 build fixesAlan Modra1-2/+2
More missing struct initialisers, for expressionS vars that in this case don't need to be initialised. Also an error: redefinition of typedef 'symbolS'. OK, so don't use a typedef.
2025-06-09aarch64: Increase the number of feature words to 3Richard Earnshaw1-1/+2
Now that most of the effort of updating the number of feature words is handled by macros, add an additional one, taking the number of supported features to 192.
2025-06-09aarch64: use macro trickery to automate feature array size replicationRichard Earnshaw1-36/+87
There are quite a few macros that need to be changed when we need to increase the number of words in the features data structure. With some macro trickery we can automate most of this so that a single macro needs to be updated. With C2X we could probably do even better by using recursion, but this is still a much better situation than we had previously. A static assertion is used to ensure that there is always enough space in the flags macro for the number of feature bits we need to support.
2025-06-09aarch64: Fix typos in opcode headersYury Khrustalev1-4/+4
2025-05-22RISC-V: Add support for Smcdeleg and Ssccfg extensions.Jiawei1-0/+4
This patch rebases the original patch from Nelson's implement[1]. Added new extension Smcdeleg and Ssccfg with a new CSR, scountinhibit.[2] Co-Authored-By: Nelson Chu <nelson@rivosinc.com> Co-Authored-By: Jiawei Chen <jiawei@iscas.ac.cn> [1] https://patchwork.sourceware.org/project/binutils/patch/20240620045359.47513-1-nelson@rivosinc.com/ [2] https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/tag/v1.0.0 bfd/ChangeLog: * elfxx-riscv.c: New extensions. gas/ChangeLog: * NEWS: Mention new extensions. * config/tc-riscv.c (enum riscv_csr_class): New CSR class. (riscv_csr_address): Add support for Ssccfg. * testsuite/gas/riscv/csr-version-1p10.d: New test for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p10.l: New warning for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p11.d: New test for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p11.l: New warning for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p12.d: New test for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p12.l: New warning for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p13.d: New test for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p13.l: New warning for Ssccfg CSR. * testsuite/gas/riscv/csr.s: New Ssccfg CSR. * testsuite/gas/riscv/imply.d: New imply check. * testsuite/gas/riscv/imply.s: New implies. * testsuite/gas/riscv/march-help.l: New helping info. include/ChangeLog: * opcode/riscv-opc.h (CSR_SCOUNTINHIBIT): New CSR address. (DECLARE_CSR): Add Ssccfg CSR.
2025-05-16RISC-V: Add zilsd & zclsd supportdysun1-0/+2
Ref: https://github.com/riscv/riscv-zilsd/blob/main/zilsd.adoc Signed-off-by: dysun <sundongya@nucleisys.com> Co-developed-by: LIU Xu <liuxu@nucleisys.com> Co-developed-by: ZHAO Fujin <zhaofujin@nucleisys.com>
2025-05-09aarch64: Eliminate AARCH64_OPND_SVE_ADDR_RAlice Carlotti1-6/+10
Adjust parsing for AARCH64_OPND_SVE_ADDR_RR{_LSL*} operands to accept implicit XZR offsets. Add new AARCH64_OPND_SVE_ADDR_RM{_LSL*} operands to support instructions where an XZR offset is allowed but must be specified explicitly. This allows the removal of the duplicate opcode table entries using AARCH64_OPND_SVE_ADDR_R.
2025-05-09RISC-V: Add Privileged Architecture 1.13 CSRs.Jiawei1-0/+4
This patch support RISC-V Privileged Architecture 1.13 CSRs 'medelegh' and 'hedelegh'. More details between 1.12 and 1.13 see [1]. [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/priv-preface.adoc Version log: Remove gas/po changes. bfd/ChangeLog: * cpu-riscv.c: New option. * cpu-riscv.h (enum riscv_spec_class): Ditto. binutils/ChangeLog: * doc/binutils.texi: New option. gas/ChangeLog: * NEWS: Add priv-1.13 support. * config/tc-riscv.c: New option. * configure: Ditto. * configure.ac: Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New CSR. * testsuite/gas/riscv/csr-version-1p10.l: New warning. * testsuite/gas/riscv/csr-version-1p11.d: New CSR. * testsuite/gas/riscv/csr-version-1p11.l: New warning. * testsuite/gas/riscv/csr-version-1p12.d: New CSR. * testsuite/gas/riscv/csr-version-1p12.l: New warning. * testsuite/gas/riscv/csr.s: New CSR. * testsuite/gas/riscv/attribute-15.d: New test. * testsuite/gas/riscv/attribute-16.d: New test. * testsuite/gas/riscv/csr-version-1p13.d: New test. * testsuite/gas/riscv/csr-version-1p13.l: New test. include/ChangeLog: * opcode/riscv-opc.h (CSR_MEDELEGH): New CSR. (CSR_HEDELEGH): Ditto. (DECLARE_CSR): Ditto.
2025-05-09RISC-V: Added vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslspChao-ying Fu2-0/+69
Spec: https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf Added MIPS vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslsp with verison 1.0. Passed binutils testsuites of targets elf32/elf64/linux32/linux64. Signed-off-by: Jovan Dmitrović <jovan.dmitrovic@htecgroup.com> Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
2025-03-26RISC-V: add Smrnmi 1.0 instruction supportJerry Zhang Jian2-0/+6
Add instruction `mnret' support Ref: https://github.com/riscv/riscv-isa-manual/blob/bb8b9127f81965eeff2d150c211d1c89376591c4/src/rnmi.adoc https://github.com/riscv/riscv-opcodes/blob/946eb673874b3a0f2474d1424dc28bc7ee53c306/extensions/rv_smrnmi bfd/ChangeLog: * elfxx-riscv.c: Add new Smrnmi instruction class handling gas/ChangeLog: * testsuite/gas/riscv/smrnmi.s: New test for mnret * testsuite/gas/riscv/rmrnmi.d: Likewise include/ChangeLog: * opcode/ricsv-opc.h: Add MATCH_MNRET, MASK_MNRET * opcode/riscv.h: Add new instruction class opcodes/ChangeLog: * riscv-opc.c: Add `mnret' instruction Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
2025-03-18RISC-V: Add extension XTheadVdot for T-Head VECTOR vendor extension [1]Jin Ma2-0/+16
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the additional extension "XTheadVdot" based on the "V" extension, and it provides four 8-bit multiply and add with 32-bit instructions for the "v" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([2]). Co-Authored-By: Lifang Xia <lifang_xia@linux.alibaba.com> [1] https://github.com/XUANTIE-RV/thead-extension-spec/tree/master/xtheadvdot [2] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add support for "XTheadVdot" extension. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: Likewise. * testsuite/gas/riscv/march-help.l: Likewise. * testsuite/gas/riscv/x-thead-vdot.d: New test. * testsuite/gas/riscv/x-thead-vdot.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VMAQA_VV): New. * opcode/riscv.h (enum riscv_insn_class): Add insn class for XTheadVdot. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2025-03-03RISC-V: Support ssqosid extension with version 1.0.Kito Cheng1-0/+4
It only add one new CSR: `srmcfg`. Ref: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
2025-01-17aarch64: Fix sve2p1 gating and add missing instructionsAndrew Carlotti1-2/+8
Many FEAT_SVE2p1 instructions need to be enabled by either of two different features (one for streaming mode, and one for non-streaming mode). This patch adds correct gating conditions for these instructions. There were also a few sve2p1 instructions missing altogether, so add those as well. The testsuite is modified to check for all alternative enablement conditions. In many cases this is done by adding an alternative assembler commands to existing test files. For some SME/SME2 tests, only some of the instructions are enabled by +sve2p1, so these are copied into a separate test. For original SVE2p1 tests, the non-SME2p1 instructions have been moved to a separate test file. There are also new tests for the newly added instructions. These include a couple of fixme comments relating to bad error reporting, which should be investigated later.
2025-01-17RISC-V: Support CFI Zicfiss and Zicfilp instructions and CSR.Monk Chiang2-0/+36
https://github.com/riscv/riscv-cfi/releases/tag/v1.0 This patch only support the CFI instructions and CSR in assembler.
2025-01-17RISC-V: Support ssctr/smctr extensions with version 1.0.Nelson Chu2-3/+18
https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0 The privileged spec v1.10 already removed the sfence.vm instruction, and the encoding of sfence.vm instruction is overlapped with the sctrclr instruction of ssctr/smctr. But since the privileged spec v1.10 already removed the sfence.vm, and we no longer support the privileged spec v1.9.1 for now, we had to remove the sfence.vm. bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Imply zicsr for ssctr/smctr. (riscv_supported_std_s_ext): Added ssctr/smctr with version 1.0. (riscv_multi_subset_supports): Handle INSN_CLASS for ssctr/smctr. (riscv_multi_subset_supports_ext): Likewise. gas/ * config/tc-riscv.c (enum riscv_csr_class, riscv_csr_address): Added and handle CSR_CLASS_SSCTR and CSR_CLASS_SMCTR. (riscv_is_priv_insn): Removed SFENCE_VM check. * testsuite/gas/riscv/attribute-14e.d: Removed since sfence.vm is no longer supported since privileged spec v1.10. * testsuite/gas/riscv/attribute-14.s: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Updated for ssctr/smctr CSRs. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr.s: Likewise. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. * testsuite/gas/riscv/march-help.l: Updated for ssctr/smctr. * testsuite/gas/riscv/smctr-ssctr.d: New testcase for sctr instruction. * testsuite/gas/riscv/smctr-ssctr.s: Likewise. include/ * opcode/riscv-opc.h: Added encoding macro for sctrclr, but removed encoding macro for sfence.vm since encoding conflict. Added CSR numbers for ssctr/smctr CSRs. * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_SMCTR_OR_SSCTR for sctrclr. opcodes/ * riscv-opc.c (riscv_opcodes): Added sctrclr, but removed sfence.vm since encoding conflict.
2025-01-10aarch64: Add support for FEAT_SME_B16B16 feature.Srinath Parvathaneni1-0/+2
This patch adds support for SME ZA-targeting non-widening BFloat16 instructions, under tick FEAT_SME_B16B16 and command line flag "+sme-b16b16". FEAT_SME_B16B16 implements FEAT_SME2 and FEAT_SVE_B16B16, in accordance with that "+sme-b16b16" enables "+sme2" and "+sve-b16b16". Also the test files related to FEAT_SME_B16B16 are prefixed with sme-b16b16*. eg: sme-b16b16-1.s, sme-b16b16-1.d. The spec for this feature and instructions is availabe here [1]: [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
2025-01-10aarch64: Add support for FEAT_SVE_B16B16 feature.Srinath Parvathaneni1-2/+2
In the current code, SVE2 Bfloat16 instructions are implemented with tick FEAT_B16B16 and command line flag "+b16b16" and this feature was suspended due to incomplete support. In the new spec available here[1], FEAT_B16B16 is replaced with FEAT_SVE_B16B16 and command line flag "+b16b16" is replace with "sve-b16b16". Also the test files related to FEAT_SVE_B16B16 are prefixed with sve-b16b16*. eg: sve-b16b16-sve2-1.s, sve-b16b16-sve2-1.d. This patch supports the SVE Z-targeting non-widening BFloat16 instructions with command line flag "+sve-b16b16+sve2". [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SVE-Instructions?lang=en
2025-01-10aarch64: Rename AARCH64_OPND_SME_ZT0_INDEX2_12Andrew Carlotti1-1/+1
Rename to AARCH64_OPND_SME_ZT0_INDEX_MUL_VL.
2025-01-10aarch64: Remove redundant sme-lutv2 qualifiers and operandsAndrew Carlotti1-1/+0
generated by cgit v1.1 at 2026-01-06 00:41:09 +0000