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AgeCommit message (Expand)AuthorFilesLines
2020-01-10ubsan: spu: left shift of negative valueAlan Modra1-17/+20
2020-01-07[ARC] Add finer details for LLOCK and SCONDShahab Vahedi1-0/+2
2020-01-02Enable building the s12z target on Solaris hosts where REG_Y is defined in sy...Nick Clifton1-10/+14
2020-01-01Update year range in copyright notice of binutils filesAlan Modra68-68/+68
2019-12-17Remove tic80 supportAlan Modra1-283/+0
2019-12-16ubsan: crx: left shift cannot be represented in type 'int'Alan Modra1-1/+1
2019-12-16ubsan: nds32: left shift cannot be represented in type 'int'Alan Modra1-3/+4
2019-12-11bfd signed overflow fixesAlan Modra1-8/+8
2019-12-11ubsan: left shift of cannot be represented in type 'int'Alan Modra1-18/+18
2019-12-05Arm64: simplify Crypto arch extension handlingJan Beulich1-1/+3
2019-11-22Arm: Change CRC from fpu feature to archititectural extensionMihail Ionescu1-16/+16
2019-11-07[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson1-0/+1
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson1-1/+9
2019-11-07[binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson1-0/+6
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson1-5/+10
2019-11-07[gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson1-1/+3
2019-09-17RISC-V: Gate opcode tables by enum rather than string.Jim Wilson1-3/+20
2019-08-30[ARC] [COMMITTED] Fix FASTMATH field.Claudiu Zissulescu1-1/+1
2019-08-08Update the handling of shift rotate and load/store multiple instructions in ...Yoshinori Sato1-47/+47
2019-07-24[ARC] Update ARC opcode tableClaudiu Zissulescu1-0/+2
2019-07-16x86: fold SReg{2,3}Jan Beulich1-0/+1
2019-07-01[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson1-1/+1
2019-05-24PowerPC add initial -mfuture instruction supportPeter Bergner1-0/+18
2019-05-16[PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fpAndre Vieira1-0/+2
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New sve_size_tsz_bhs iclass.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New sve_shift_tsz_bhsd iclass.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson1-0/+2
2019-05-09[binutils][aarch64] New sve_size_013 iclass.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New sve_size_bh iclass.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New sve_size_sd2 iclass.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New iclass sve_size_hsd2.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] SVE2 feature extension flags.Matthew Malcomson1-0/+7
2019-05-06Add load-link, store-conditional paired EVA instructionsFaraz Shahbazker1-0/+5
2019-05-01[BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das1-1/+3
2019-04-26[MIPS] Add load-link, store-conditional paired instructionsAndrew Bennett1-0/+4
2019-04-25MIPS/include: opcode/mips.h: Update stale comment for CODE20 operandMaciej W. Rozycki1-2/+2
2019-04-15[binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLIAndre Vieira1-0/+6
2019-04-11[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructionsSudakshina Das1-0/+1
2019-04-01[GAS, Arm] CLI with architecture sensitive extensionsAndre Vieira1-7/+24
2019-03-28PR24390, Don't decode mtfsb field as a cr fieldAlan Modra1-1/+4
2019-01-31S/390: Implement instruction set extensionsAndreas Krebbel1-0/+1
2019-01-25AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte...Sudi Das1-2/+0
2019-01-05RX: include - Add RXv3 support.Yoshinori Sato1-0/+32
2019-01-01Update year range in copyright notice of binutils filesAlan Modra69-69/+69
2018-12-28PR24028, PPC_INT_FMTAlan Modra1-8/+0