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authorMatthew Malcomson <matthew.malcomson@arm.com>2019-05-09 10:29:15 +0100
committerMatthew Malcomson <matthew.malcomson@arm.com>2019-05-09 10:29:15 +0100
commitadccc50753467ac66573471f180a60d8d96ce223 (patch)
treec3f8777976a8b215ea877ac790918e5ee90d2e5a /include/opcode
parent5cd99750959f54fea9e7290ec850df6c96878b56 (diff)
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[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.
New operand AARCH64_OPND_SVE_IMM_ROT3 handles a single bit rotate operand encoded at bit position 10. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_IMM_ROT3. (aarch64_print_operand): Add printing for SVE_IMM_ROT3. (fields): Handle SVE_rot3 field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
Diffstat (limited to 'include/opcode')
-rw-r--r--include/opcode/aarch64.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index fdc7cde..e392499 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -372,6 +372,7 @@ enum aarch64_opnd
AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
+ AARCH64_OPND_SVE_IMM_ROT3, /* SVE cadd 1-bit rotate (90 or 270). */
AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */