riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-01-08	arm: Add support for Armv8.9-A and Armv9.4-A	srinath	1	-0/+2
2024-01-05	RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvli	Jin Ma	1	-0/+11
2024-01-04	Update year range in copyright notice of binutils files	Alan Modra	72	-72/+72
2023-12-28	Support APX GPR32 with rex2 prefix	Cui, Lili	1	-0/+4
2023-12-25	LoongArch: Add tls transition support.	Lulu Cai	1	-0/+6
2023-12-20	s390: Optionally print instruction description in disassembly	Jens Remus	1	-1/+4
2023-12-19	aarch64: Add FEAT_ITE support	Andrea Corallo	1	-0/+2
2023-12-19	aarch64: Add FEAT_SPECRES2 support	Andrea Corallo	1	-1/+4
2023-12-14	RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.	Jin Ma	1	-4/+4
2023-12-04	s390: Support for jump visualization in disassembly	Jens Remus	1	-3/+22
2023-12-01	RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0	Nelson Chu	2	-0/+64
2023-12-01	RISC-V: Zv*: Add support for Zvkb ISA extension	Christoph Müllner	2	-2/+3
2023-11-24	RISC-V: reduce redundancy in sign/zero extension macro insn handling	Jan Beulich	1	-2/+1
2023-11-23	RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+10
2023-11-23	RISC-V: Add vector mask instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+14
2023-11-23	RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor e...	Jin Ma	1	-0/+36
2023-11-23	RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor exte...	Jin Ma	1	-0/+12
2023-11-23	RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+12
2023-11-23	RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extension	Jin Ma	2	-1/+37
2023-11-23	RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+169
2023-11-23	RISC-V: Add load/store instructions for T-Head VECTOR vendor extension	Jin Ma	1	-0/+33
2023-11-23	RISC-V: Add CSRs for T-Head VECTOR vendor extension	Jin Ma	1	-0/+7
2023-11-23	RISC-V: Add T-Head VECTOR vendor extension.	Jin Ma	1	-0/+1
2023-11-16	aarch64: Add support for VMSA feature enhancements.	Srinath Parvathaneni	1	-1/+20
2023-11-16	aarch64: Add new AT system instructions.	Srinath Parvathaneni	1	-1/+4
2023-11-16	aarch64: Add support to new features in RAS extension.	Srinath Parvathaneni	1	-1/+13
2023-11-16	aarch64: Add features to the Statistical Profiling Extension.	Srinath Parvathaneni	1	-1/+10
2023-11-10	Add support for ilp32 register alias.	Lulu Cai	1	-4/+4
2023-11-07	aarch64: Add arch support for LSE128 extension	Victor Do Nascimento	1	-0/+3
2023-11-07	aarch64: Add LSE128 instruction operand support	Victor Do Nascimento	1	-0/+2
2023-11-07	aarch64: Add THE system register support	Victor Do Nascimento	1	-0/+2
2023-11-07	RISC-V: Add support for XCValu extension in CV32E40P	Mary Bennett	2	-0/+72
2023-11-07	RISC-V: Add support for XCVmac extension in CV32E40P	Mary Bennett	2	-0/+44
2023-11-03	RISC-V: reduce redundancy in load/store macro insn handling	Jan Beulich	1	-19/+3
2023-11-02	aarch64: Add support for GCSB DSYNC instruction.	Srinath Parvathaneni	1	-0/+2
2023-11-02	aarch64: Add support for GCS extension.	srinath	1	-1/+3
2023-11-02	aarch64: Add support for Check Feature Status Extension.	Srinath Parvathaneni	1	-2/+5
2023-11-02	aarch64: Add support for Armv8.9-A and Armv9.4-A Architectures.	srinath	1	-1/+8
2023-10-19	RISC-V: Remove semicolons from DECLARE_INSN	Tsukasa OI	1	-15/+15
2023-10-17	RISC-V: Fix typo	Tsukasa OI	1	-1/+1
2023-10-10	LoongArch/GAS: Add support for branch relaxation	mengqinggang	1	-0/+12
2023-10-08	as: add option for generate R_LARCH_32/64_PCREL.	cailulu	1	-0/+1
2023-10-04	aarch64: system register aliasing detection	Victor Do Nascimento	1	-0/+1
2023-09-26	aarch64: Allow feature flags to occupy >64 bits	Richard Sandiford	1	-23/+39
2023-09-26	aarch64: Restructure feature flag handling	Richard Sandiford	1	-151/+268
2023-09-25	Revert "arc: Update opcode related include files for ARCv3."	Claudiu Zissulescu	3	-257/+56
2023-09-25	arc: Update opcode related include files for ARCv3.	Claudiu Zissulescu	3	-56/+257
2023-09-05	RISC-V: fold duplicate code in vector_macro()	Jan Beulich	1	-1/+0
2023-09-05	RISC-V: Add 'Smcntrpmf' extension and its CSRs	Tsukasa OI	1	-4/+12
2023-08-22	aarch64: Improve naming conventions for A and R-profile architecture	Victor Do Nascimento	1	-54/+54