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| author | Jin Ma <jinma@linux.alibaba.com> | 2023-11-18 15:07:20 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2023-11-23 09:31:57 +0800 |
| commit | 9a51da2636778dce2e2635cb10822a92a51b2b9e (patch) | |
| tree | d4e22f44aa8a8a61acdf142647fec1bd2eeff7e4 /include/opcode | |
| parent | c63af675b9b69abbbf5e48d7b77ec2d311c5b6a8 (diff) | |
| download | gdb-9a51da2636778dce2e2635cb10822a92a51b2b9e.zip gdb-9a51da2636778dce2e2635cb10822a92a51b2b9e.tar.gz gdb-9a51da2636778dce2e2635cb10822a92a51b2b9e.tar.bz2 | |
RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds fixed-point arithmetic instructions for the
"XTheadVector" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add tests for
fixed-point arithmetic instructions.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VAADDVV): New.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/riscv-opc.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index df4b7ab..5cca4c5 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2897,6 +2897,18 @@ #define MASK_TH_VSBCVXM 0xfe00707f #define MATCH_TH_VWMACCSUVV 0xf8002057 #define MASK_TH_VWMACCSUVV 0xfc00707f +#define MATCH_TH_VAADDVV 0x90000057 +#define MASK_TH_VAADDVV 0xfc00707f +#define MATCH_TH_VAADDVX 0x90004057 +#define MASK_TH_VAADDVX 0xfc00707f +#define MATCH_TH_VAADDVI 0x90003057 +#define MASK_TH_VAADDVI 0xfc00707f +#define MATCH_TH_VASUBVV 0x98000057 +#define MASK_TH_VASUBVV 0xfc00707f +#define MATCH_TH_VASUBVX 0x98004057 +#define MASK_TH_VASUBVX 0xfc00707f +#define MATCH_TH_VWSMACCSUVV 0xf8000057 +#define MASK_TH_VWSMACCSUVV 0xfc00707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f |