Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2017-06-30 | MIPS: Fix XPA base and Virtualization ASE instruction handling | Maciej W. Rozycki | 1 | -0/+3 |
2017-06-28 | MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support | Maciej W. Rozycki | 1 | -5/+16 |
2017-05-15 | MIPS16e2: Add MIPS16e2 ASE support | Maciej W. Rozycki | 1 | -5/+34 |
2017-01-02 | Update year range in copyright notice of all files. | Alan Modra | 1 | -1/+1 |
2016-12-23 | MIPS16: Add ASMACRO instruction support | Maciej W. Rozycki | 1 | -2/+8 |
2016-12-23 | MIPS16: Reassign `0' and `4' operand codes | Maciej W. Rozycki | 1 | -5/+5 |
2016-12-23 | MIPS16: Handle non-extensible instructions correctly | Maciej W. Rozycki | 1 | -0/+4 |
2016-12-20 | MIPS16: Switch to 32-bit opcode table interpretation | Maciej W. Rozycki | 1 | -0/+8 |
2016-12-09 | MIPS16: Remove unused `>' operand code | Maciej W. Rozycki | 1 | -2/+1 |
2016-12-07 | MIPS/include: opcode/mips.h: Correct INSN_CHIP_MASK | Maciej W. Rozycki | 1 | -1/+1 |
2016-12-07 | MIPS/include: opcode/mips.h: Add a comment for ASE_DSPR3 | Maciej W. Rozycki | 1 | -0/+1 |
2016-06-01 | add more extern C | Trevor Saunders | 1 | -0/+8 |
2016-05-11 | Add MIPS32 DSPr3 support. | Matthew Fortune | 1 | -0/+1 |
2016-01-06 | MIPS/include: opcode/mips.h: Add a summary of MIPS16 operand codes | Maciej W. Rozycki | 1 | -0/+6 |
2016-01-01 | Copyright update for binutils | Alan Modra | 1 | -1/+1 |
2015-01-02 | ChangeLog rotatation and copyright year update | Alan Modra | 1 | -1/+1 |
2014-10-31 | MIPS: Add Octeon 3 support | Naveen H.S | 1 | -0/+5 |
2014-09-15 | Add support for MIPS R6. | Andrew Bennett | 1 | -8/+93 |
2014-08-26 | MIPS: Make the CODE10 operand code consistent between ISAs | Maciej W. Rozycki | 1 | -3/+4 |
2014-07-29 | [MIPS] Rename COPROC related macros | Matthew Fortune | 1 | -4/+4 |
2014-05-07 | Add MIPS r3 and r5 support. | Andrew Bennett | 1 | -9/+30 |
2014-05-01 | include/opcode/ | Richard Sandiford | 1 | -10/+27 |
2014-04-23 | Add support for the MIPS eXtended Physical Address (XPA) ASE. | Andrew Bennett | 1 | -0/+2 |
2014-03-05 | Update copyright years | Alan Modra | 1 | -3/+1 |
2013-12-16 | Range of element index is too large on MIPS MSA element selection instructions. | Andrew Bennett | 1 | -8/+8 |
2013-11-11 | 2013-11-11 Catherine Moore <clm@codesourcery.com> | Catherine Moore | 1 | -2/+2 |
2013-10-14 | 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> | Chao-ying Fu | 1 | -7/+76 |
2013-08-19 | include/opcode/ | Richard Sandiford | 1 | -4/+2 |
2013-08-19 | include/opcode/ | Richard Sandiford | 1 | -2/+0 |
2013-08-19 | include/opcode/ | Richard Sandiford | 1 | -0/+13 |
2013-08-04 | include/opcode/ | Richard Sandiford | 1 | -6/+49 |
2013-08-03 | include/opcode/ | Richard Sandiford | 1 | -11/+24 |
2013-08-01 | include/opcode/ | Richard Sandiford | 1 | -121/+62 |
2013-08-01 | include/opcode/ | Richard Sandiford | 1 | -10/+0 |
2013-07-14 | include/opcode/ | Richard Sandiford | 1 | -0/+8 |
2013-07-14 | include/opcode/ | Richard Sandiford | 1 | -0/+288 |
2013-07-14 | include/opcode/ | Richard Sandiford | 1 | -0/+2 |
2013-07-07 | include/opcode/ | Richard Sandiford | 1 | -90/+9 |
2013-07-07 | include/opcode/ | Richard Sandiford | 1 | -10/+8 |
2013-07-07 | include/opcode/ | Richard Sandiford | 1 | -5/+4 |
2013-07-07 | include/opcode/ | Richard Sandiford | 1 | -3/+6 |
2013-07-07 | include/opcode/ | Richard Sandiford | 1 | -9/+3 |
2013-07-07 | include/opcode/ | Richard Sandiford | 1 | -7/+2 |
2013-06-26 | include/opcode/ | Richard Sandiford | 1 | -4/+4 |
2013-06-25 | bfd/ | Maciej W. Rozycki | 1 | -0/+3 |
2013-06-23 | include/opcode/ | Richard Sandiford | 1 | -1/+1 |
2013-06-17 | 2013-06-17 Catherine Moore <clm@codesourcery.com> | Catherine Moore | 1 | -5/+50 |
2013-06-08 | gas/ | Richard Sandiford | 1 | -23/+23 |
2013-05-22 | include/opcode/ | Richard Sandiford | 1 | -0/+2 |
2013-05-10 | binutils/ChangeLog: | Andrew Pinski | 1 | -4/+13 |