aboutsummaryrefslogtreecommitdiff
path: root/include/opcode/mips.h
AgeCommit message (Expand)AuthorFilesLines
2021-05-29MIPS/opcodes: Properly handle ISA exclusionMaciej W. Rozycki1-19/+18
2021-05-29MIPS/opcodes: Factor out ISA matching against flagsMaciej W. Rozycki1-4/+21
2021-05-29MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki1-2/+9
2021-05-29MIPS/opcodes: Free up redundant `g' operand codeMaciej W. Rozycki1-2/+1
2021-03-31Use bool in includeAlan Modra1-17/+17
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-05-06Add load-link, store-conditional paired EVA instructionsFaraz Shahbazker1-0/+5
2019-04-26[MIPS] Add load-link, store-conditional paired instructionsAndrew Bennett1-0/+4
2019-04-25MIPS/include: opcode/mips.h: Update stale comment for CODE20 operandMaciej W. Rozycki1-2/+2
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-08-29[MIPS] Add Loongson 2K1000 proccessor support.Chenghua Xu1-0/+1
2018-08-29[MIPS] Add Loongson 3A2000/3A3000 proccessor support.Chenghua Xu1-0/+1
2018-08-29[MIPS] Add Loongson 3A1000 proccessor support.Chenghua Xu1-7/+2
2018-08-29[MIPS/GAS] Add Loongson EXT2 Instructions support.Chenghua Xu1-0/+2
2018-08-29[MIPS/GAS] Split Loongson EXT Instructions from loongson3a.Chenghua Xu1-0/+2
2018-08-29[MIPS/GAS] Split Loongson CAM Instructions from loongson3aChenghua Xu1-0/+2
2018-07-20MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3aChenghua Xu1-0/+2
2018-06-14MIPS: Add Global INValidate ASE supportFaraz Shahbazker1-1/+6
2018-06-13MIPS: Add CRC ASE supportScott Egerton1-0/+3
2018-02-20MIPS16/opcodes: Free up `M' operand codeMaciej W. Rozycki1-3/+2
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-06-30MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki1-0/+3
2017-06-28MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki1-5/+16
2017-05-15MIPS16e2: Add MIPS16e2 ASE supportMaciej W. Rozycki1-5/+34
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-23MIPS16: Add ASMACRO instruction supportMaciej W. Rozycki1-2/+8
2016-12-23MIPS16: Reassign `0' and `4' operand codesMaciej W. Rozycki1-5/+5
2016-12-23MIPS16: Handle non-extensible instructions correctlyMaciej W. Rozycki1-0/+4
2016-12-20MIPS16: Switch to 32-bit opcode table interpretationMaciej W. Rozycki1-0/+8
2016-12-09MIPS16: Remove unused `>' operand codeMaciej W. Rozycki1-2/+1
2016-12-07MIPS/include: opcode/mips.h: Correct INSN_CHIP_MASKMaciej W. Rozycki1-1/+1
2016-12-07MIPS/include: opcode/mips.h: Add a comment for ASE_DSPR3Maciej W. Rozycki1-0/+1
2016-06-01add more extern CTrevor Saunders1-0/+8
2016-05-11Add MIPS32 DSPr3 support.Matthew Fortune1-0/+1
2016-01-06MIPS/include: opcode/mips.h: Add a summary of MIPS16 operand codesMaciej W. Rozycki1-0/+6
2016-01-01Copyright update for binutilsAlan Modra1-1/+1
2015-01-02ChangeLog rotatation and copyright year updateAlan Modra1-1/+1
2014-10-31MIPS: Add Octeon 3 supportNaveen H.S1-0/+5
2014-09-15Add support for MIPS R6.Andrew Bennett1-8/+93
2014-08-26MIPS: Make the CODE10 operand code consistent between ISAsMaciej W. Rozycki1-3/+4
2014-07-29[MIPS] Rename COPROC related macrosMatthew Fortune1-4/+4
2014-05-07Add MIPS r3 and r5 support.Andrew Bennett1-9/+30
2014-05-01include/opcode/Richard Sandiford1-10/+27
2014-04-23Add support for the MIPS eXtended Physical Address (XPA) ASE.Andrew Bennett1-0/+2
2014-03-05Update copyright yearsAlan Modra1-3/+1
2013-12-16Range of element index is too large on MIPS MSA element selection instructions.Andrew Bennett1-8/+8
2013-11-112013-11-11 Catherine Moore <clm@codesourcery.com>Catherine Moore1-2/+2
2013-10-142013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>Chao-ying Fu1-7/+76
2013-08-19include/opcode/Richard Sandiford1-4/+2
generated by cgit v1.1 at 2024-12-18 04:57:34 +0000