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path: root/gdb/riscv-tdep.c
AgeCommit message (Expand)AuthorFilesLines
2019-01-03RISC-V: Fix wrong use of s0 register name.Jim Wilson1-1/+1
2019-01-01gdb/riscv: Split ISA and ABI featuresAndrew Burgess1-37/+44
2019-01-01Update copyright year range in all GDB files.Joel Brobecker1-1/+1
2018-12-22gdb/riscv: Prevent buffer overflow in riscv_return_valueAndrew Burgess1-6/+59
2018-12-22gdb/riscv: Add float status registers to save and restore reggroupsAndrew Burgess1-1/+4
2018-12-22gdb/riscv: Add gdb to dwarf register number mappingAndrew Burgess1-0/+17
2018-12-21gdb/riscv: Format CORE_ADDR as a string for printingAndrew Burgess1-4/+10
2018-12-13RISC-V: Correct printing of MSTATUS and MISA.Jim Wilson1-2/+8
2018-12-12gdb/riscv: Handle passing variadic floating point argumentsAndrew Burgess1-2/+3
2018-12-10gdb/riscv: Remove whitespace before #include lineAndrew Burgess1-1/+1
2018-12-05gdb/riscv: Improve logic for when h/w float abi should be usedAndrew Burgess1-12/+49
2018-11-30gdb/riscv: Add equality operators to riscv_gdb_featuresAndrew Burgess1-3/+1
2018-11-30gdb/riscv: Make some target description functions constantAndrew Burgess1-1/+1
2018-11-21gdb/riscv: Add target description supportAndrew Burgess1-351/+537
2018-11-16Pass return_method to _push_dummy_callAlan Hayward1-4/+4
2018-11-14RISC-V: Fix unnamed arg alignment in registers.Jim Wilson1-4/+22
2018-11-14RISC-V: Handle vector type alignment.Jim Wilson1-0/+7
2018-11-14RISC-V: Give stack slots same align as XLEN.Jim Wilson1-2/+3
2018-11-08gdb/riscv: Handle errors while setting the frame idAndrew Burgess1-3/+14
2018-11-01RISC-V: Don't allow unaligned breakpoints.Jim Wilson1-8/+24
2018-10-26RISC-V: Linux signal frame support.Jim Wilson1-8/+3
2018-10-26gdb/riscv: Remove redundant code, and catch more errors when accessing MISAAndrew Burgess1-22/+29
2018-10-23gdb/riscv: Give user-friendly names for CSRsAndrew Burgess1-4/+15
2018-10-23gdb/riscv: expect h/w watchpoints to trigger before the memory is writtenJoel Brobecker1-0/+1
2018-10-23gdb/riscv: Fix register access for register aliasesAndrew Burgess1-105/+116
2018-10-22RISC-V: NaN-box FP values smaller than an FP register.Jim Wilson1-2/+12
2018-10-22RISC-V: Print FP regs as union of float types.Jim Wilson1-3/+82
2018-10-04Simple -Wshadow=local fixesTom Tromey1-4/+2
2018-09-28Use the existing instruction to determine the RISC-V breakpoint kind.John Baldwin1-17/+32
2018-09-26gdb/riscv: Improve non-dwarf stack unwindingAndrew Burgess1-21/+38
2018-09-04gdb/riscv: Fix an ARI warningAndrew Burgess1-2/+2
2018-09-03gdb/riscv: Provide non-DWARF stack unwinderAndrew Burgess1-47/+180
2018-08-30gdb/riscv: Extend instruction decode to cover more instructionsAndrew Burgess1-2/+38
2018-08-30gdb/riscv: remove extra caching of misa registerAndrew Burgess1-101/+5
2018-08-08RISC-V: Add software single step support.Jim Wilson1-6/+244
2018-08-08RISC-V: Make riscv_isa_xlen a global function.Jim Wilson1-1/+1
2018-07-22Simple unused variable removalsTom Tromey1-7/+0
2018-07-17RISC-V: Don't decrement pc after break.Jim Wilson1-23/+2
2018-07-16RISC-V: Add osabi support.Jim Wilson1-0/+3
2018-07-10gdb/riscv: Fix assertion in inferior call codeAndrew Burgess1-5/+16
2018-07-10gdb/riscv: Use TYPE_SAFE_NAMEAndrew Burgess1-5/+1
2018-07-02gdb: Prefer RISC-V register name "s0" over "fp"Sebastian Huber1-1/+1
2018-05-30Remove regcache_cooked_writeSimon Marchi1-9/+5
2018-05-30Remove regcache_cooked_readSimon Marchi1-2/+2
2018-05-04Fix "obvious" fall-through warningsTom Tromey1-0/+1
2018-03-19Convert observers to C++Tom Tromey1-3/+3
2018-03-12gdb/riscv: Fix some ARI issuesAndrew Burgess1-9/+8
2018-03-06gdb/riscv: Remove partial target description supportAndrew Burgess1-37/+0
2018-03-06gdb/riscv: Remove 'Contributed by....' commentsAndrew Burgess1-5/+0
2018-03-06gdb/riscv: Remove use of pseudo registersAndrew Burgess1-25/+0
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