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| author | Jim Wilson <jimw@sifive.com> | 2018-12-13 10:48:23 -0800 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2018-12-13 10:48:23 -0800 |
| commit | b7c8601a7f2874de1bbe0dc38ef86ea053593ad8 (patch) | |
| tree | 4bec21273d6338db77a47fb9aeaabc743fe7caea /gdb/riscv-tdep.c | |
| parent | 09038062534606ef9100b5474d136f7d2e543de4 (diff) | |
| download | gdb-b7c8601a7f2874de1bbe0dc38ef86ea053593ad8.zip gdb-b7c8601a7f2874de1bbe0dc38ef86ea053593ad8.tar.gz gdb-b7c8601a7f2874de1bbe0dc38ef86ea053593ad8.tar.bz2 | |
RISC-V: Correct printing of MSTATUS and MISA.
* riscv-tdep.c (riscv_print_one_register_info): For MSTATUS, add
comment for SD field, and correct xlen calculation. For MISA, add
comment for MXL field, add call to register_size, and correct base
calculation.
Diffstat (limited to 'gdb/riscv-tdep.c')
| -rw-r--r-- | gdb/riscv-tdep.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index fc424fb..88b79af 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -701,8 +701,10 @@ riscv_print_one_register_info (struct gdbarch *gdbarch, int size = register_size (gdbarch, regnum); unsigned xlen; + /* The SD field is always in the upper bit of MSTATUS, regardless + of the number of bits in MSTATUS. */ d = value_as_long (val); - xlen = size * 4; + xlen = size * 8; fprintf_filtered (file, "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X " "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X " @@ -731,9 +733,13 @@ riscv_print_one_register_info (struct gdbarch *gdbarch, int base; unsigned xlen, i; LONGEST d; + int size = register_size (gdbarch, regnum); + /* The MXL field is always in the upper two bits of MISA, + regardless of the number of bits in MISA. Mask out other + bits to ensure we have a positive value. */ d = value_as_long (val); - base = d >> 30; + base = (d >> ((size * 8) - 2)) & 0x3; xlen = 16; for (; base > 0; base--) |