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2019-05-16[PATCH 4/57][Arm][GAS] Add support for MVE instructions: vabav, vmladav and v...Andre Vieira14-3/+488
2019-05-16[PATCH 3/57][Arm][GAS] Add support for MVE instructions: vabs and vnegAndre Vieira8-6/+161
2019-05-16[PATCH 2/57][Arm][GAS] Add support for MVE instructions: vpst, vadd, vsub and...Andre Vieira16-353/+1328
2019-05-16[PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fpAndre Vieira3-1/+30
2019-05-15S12Z: New option -mreg-prefixJohn Darrington6-17/+155
2019-05-15GAS (doc): Fix misaligned menu entry.John Darrington2-1/+5
2019-05-15C-SKY FAIL: jbt - cskyAlan Modra2-0/+7
2019-05-15.file file number checkingAlan Modra2-22/+31
2019-05-15tic54x_start_line_hookAlan Modra2-6/+9
2019-05-14Fix illegal memory access triggered when attempting to assemble a bogus i386 ...Nick Clifton2-0/+12
2019-05-14A series of fixes to addres problems detected by compiling the assembler with...Nick Clifton29-138/+168
2019-05-10Add macro expansions for ADD, SUB, DADD and DSUB for MIPS r6Faraz Shahbazker7-10/+62
2019-05-09Update printing of optional operands during disassembly.Peter Bergner2-4/+4
2019-05-09[gas][testsuite] Don't specify arch in testsuite outputMatthew Malcomson2-1/+5
2019-05-09[binutils][aarch64] Add SVE2 testsMatthew Malcomson13-0/+8621
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson2-0/+6
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson2-0/+6
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson2-0/+6
2019-05-09[binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson2-4/+54
2019-05-09[binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson2-0/+6
2019-05-09[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson2-0/+5
2019-05-09[binutils][aarch64] SVE2 feature extension flags.Matthew Malcomson3-0/+29
2019-05-08gas/elf dwarf2 testsAlan Modra35-220/+243
2019-05-08xtensa ignores option --no-link-relaxAlan Modra2-3/+10
2019-05-07xfail locview tests on mep that use complex relocs for view numbersAlexandre Oliva3-2/+9
2019-05-07Tidy use_complex_relocs_forAlan Modra2-22/+18
2019-05-06Add load-link, store-conditional paired EVA instructionsFaraz Shahbazker6-1/+91
2019-05-06sym->sy_value is not valid for struct local_symbolAlan Modra2-1/+6
2019-05-06PowerPC reloc symbols that shouldn't be adjustedAlan Modra3-1/+27
2019-05-05[LVu] base subseg head view on prev subseg's tailAlexandre Oliva5-5/+107
2019-05-04m32c padding with nopsAlan Modra8-31/+23
2019-05-02i386: Issue a warning to IRET without suffix for .code16gccH.J. Lu5-7/+46
2019-05-01[BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das8-0/+111
2019-04-29S12Z: Opcodes: Fix crash when trying to decode a truncated operation.John Darrington4-0/+27
2019-04-26[MIPS] Add load-link, store-conditional paired instructionsAndrew Bennett14-10/+228
2019-04-26i386: Don't add 0x66 prefix to IRET for .code16gccH.J. Lu4-0/+22
2019-04-25Speed up locview resolution with relaxable fragsAlexandre Oliva4-1/+69
2019-04-24resolve_symbol_value vs. .loc view resolutionAlan Modra3-29/+35
2019-04-24S12Z: Opcodes: Handle bit map operations with non-canonical operands.John Darrington3-1/+15
2019-04-19RX Assembler: Ensure that the internal limit on the number of relaxation iter...Nick Clifton3-8/+31
2019-04-18Improve warning message for $0 constraint on MIPSR6 branchesMatthew Fortune3-11/+20
2019-04-18MSP430 Assembler: Define symbols for functions to run through.Jozef Lawrynowicz9-6/+141
2019-04-17MSP430 Assembler: Leave placement of .lower and .upper sections to generic li...Jozef Lawrynowicz1-0/+13
2019-04-17MSP420 assembler: Add -m{u,U} options to enable/disable NOP warnings for unk...Jozef Lawrynowicz13-10/+198
2019-04-16xfail gas weakref1 test for nds32Alan Modra2-0/+5
2019-04-16ns32k testsuite tidyAlan Modra3-3/+6
2019-04-16Move fixup fx_bit_fixP and fx_im_disp fields to TC_FIX_TYPEAlan Modra8-68/+66
2019-04-16Make fixup fx_where unsignedAlan Modra7-27/+36
2019-04-16Make frag fr_fix unsignedAlan Modra13-23/+40
2019-04-15[binutils, ARM, 16/16] Add support to VLDR and VSTR of system registersAndre Vieira6-4/+225
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