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2024-07-05aarch64: add STEP2 feature and its associated registersMatthieu Longo3-0/+9
2024-07-05aarch64: add SPMU2 feature and its associated registersMatthieu Longo3-0/+9
2024-07-05aarch64: add E3DSE feature and its associated registersMatthieu Longo4-0/+32
2024-07-05x86-64: Fix support for APX NF TLS IE with 2 operandsLingling Kong1-3/+2
2024-07-05aarch64: fix build with old glibcJan Beulich1-3/+3
2024-07-05x86: Correct position of ".s" for CCMPcc in disassemblerCui, Lili2-3/+12
2024-07-05x86: Add {load}/{store} tests for apx instructions.Cui, Lili3-0/+204
2024-07-04RISC-V: Fix BFD_RELOC_RISCV_PCREL_LO12_S patch issueSun Sunny4-40/+114
2024-07-04RISC-V: hash with segment id and pcrel_hi address while recording pcrel_hiLifang Xia1-7/+17
2024-07-04mve: Fix encoding for vcvt[bt] single-half float conversion instructionsAndre Vieira2-72/+81
2024-07-04gas: Validate SFrame RA tracking and fixed RA offsetJens Remus1-5/+9
2024-07-04gas: Test predicate whether SFrame RA tracking is usedJens Remus1-2/+4
2024-07-04gas: Don't skip SFrame FDE if .cfi_register specifies SP registerJens Remus1-3/+6
2024-07-04gas: Don't skip SFrame FDE if .cfi_register specifies RA w/o trackingJens Remus1-1/+1
2024-07-04gas: Skip SFrame FDE if .cfi_window_saveJens Remus1-3/+22
2024-07-04gas: Skip SFrame FDE if FP without RA on stackJens Remus1-2/+19
2024-07-04gas: User readable warnings if SFrame FDE is not generatedJens Remus5-28/+72
2024-07-04gas: Refactor SFrame CFI opcode DW_CFA_register processingJens Remus1-11/+26
2024-07-04gas: Warn if SFrame FDE is skipped due to non-default return columnJens Remus2-3/+8
2024-07-04gas: Skip SFrame FDE if CFI specifies non-FP/SP base registerJens Remus1-2/+11
2024-07-04gas: Print DWARF call frame insn name in SFrame warning messageJens Remus3-3/+50
2024-07-04readelf/objdump: Display SFrame fixed RA offset as 'f' in dumpJens Remus8-23/+23
2024-07-04readelf/objdump: Dump SFrame CFA fixed FP and RA offsetsJens Remus14-0/+25
2024-07-04gas: Enhance arch-specific SFrame configuration descriptionsJens Remus4-14/+19
2024-07-04x86: Remove unused SFrame CFI RA register variableJens Remus1-1/+0
2024-07-04Support APX CFCMOVCui, Lili7-5/+401
2024-07-03RISC-V: Tidy and complete testing of all architecture imply rules.Nelson Chu21-97/+177
2024-07-03Avoid possible signed overflow in decode_local_label_nameAlan Modra1-4/+4
2024-07-03gas/doc/riscv: Fixed typo of `.insn cj' formatNelson Chu1-1/+1
2024-07-03x86-64: Support APX NF TLS IE with 2 operandsLingling Kong3-2/+22
2024-07-03gas/doc/riscv: Fixed syntax of `.option arch' when reseting whole architectureNelson Chu1-2/+2
2024-07-01x86-64: Verify that TLS IE works with APX NFkonglin12-2/+10
2024-06-28aarch64: Add support for Armv9.5-A architectureClaudio Bantaloukas12-4/+34
2024-06-28x86/APX: apply NDD-to-legacy transformation to further CMOVcc formsJan Beulich3-1/+48
2024-06-28x86/APX: extend TEST-by-imm7 optimization to CTESTccJan Beulich4-18/+118
2024-06-28x86/APX: optimize {nf}-form IMUL-by-power-of-2 to SHLJan Beulich4-0/+252
2024-06-28x86-64: restrict by-imm31 optimizationJan Beulich4-18/+21
2024-06-28x86/APX: optimize certain {nf}-form insns to LEAJan Beulich5-8/+1812
2024-06-28x86/APX: optimize {nf}-form rotate-by-width-less-1Jan Beulich3-1/+73
2024-06-28x86/APX: optimize {nf} forms of ADD/SUB with specific immediatesJan Beulich6-2/+1628
2024-06-28gas: .irp/.irpc are macro-likeJan Beulich1-2/+2
2024-06-28RISC-V: Add Zabha extension CAS instructions.Jiawei3-2/+26
2024-06-26aarch64: FP8 scale and convert - Implement minor improvementsVictor Do Nascimento6-201/+166
2024-06-25aarch64: Treat operand ADDR_SIMPLE as address with base registerJens Remus1-3/+3
2024-06-25aarch64: Fix FEAT_B16B16 sve2 instruction constraints.Srinath Parvathaneni12-26/+456
2024-06-25aarch64: Add extra tests for sve2p1 min max instructions.Srinath Parvathaneni6-201/+524
2024-06-25arch64: Fix the wrong constraint used for sve2p1 instructions.Srinath Parvathaneni3-0/+131
2024-06-25aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.Srinath Parvathaneni13-118/+630
2024-06-25aarch64: Fix sve2p1 extq instruction operands.Srinath Parvathaneni9-19/+87
2024-06-25aarch64: Fix sve2p1 dupq instruction operands.Srinath Parvathaneni6-7/+129
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