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2021-06-08x86: cover a.out in recently added testsJan Beulich4-41/+47
2021-06-08x86: minor improvements to optimize_imm() (part II)Jan Beulich2-3/+7
2021-06-08x86: minor improvements to optimize_disp() (part II)Jan Beulich2-7/+10
2021-06-08x86-64: avoid bogus warnings with 32-bit addressingJan Beulich9-0/+89
2021-06-08x86: minor improvements to optimize_disp() (part I)Jan Beulich2-11/+18
2021-06-07x86: honor quoted figure braces in i386_att_operand()Jan Beulich4-8/+43
2021-06-07x86: better respect quotes in parse_operands()Jan Beulich4-14/+40
2021-06-07x86: allow unary operators to start a memory operandJan Beulich5-14/+40
2021-06-07x86: make symbol quotation check consistent in i386_att_operand()Jan Beulich5-7/+44
2021-06-07x86: correct absolute branch check with segment overrideJan Beulich2-9/+14
2021-06-07x86/Intel: drop unnecessary bracket matching from parse_operands()Jan Beulich2-13/+8
2021-06-07x86: remove pointless 2nd parameter from check_VecOperations()Jan Beulich3-6/+11
2021-06-07x86: immediate operands don't allow for vector operationsJan Beulich2-10/+4
2021-06-07ix86: wrap constantsJan Beulich6-6/+165
2021-06-03PR1202, mcore disassembler: wrong address looptAlan Modra2-1/+6
2021-05-29PowerPC table driven -Mraw disassemblyAlan Modra4-0/+121
2021-05-29MIPS/GAS/testsuite: Add C0, C1, C2, C3 opcode testsMaciej W. Rozycki54-0/+7580
2021-05-29MIPS/GAS/testsuite: Run RFE test across all ISAsMaciej W. Rozycki8-7/+39
2021-05-29MIPS/GAS/testsuite: Run coprocessor tests across all ISAsMaciej W. Rozycki96-467/+1646
2021-05-29MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membershipMaciej W. Rozycki3-2/+53
2021-05-29MIPS/GAS/testsuite: Add tests for coprocessor branch instructionsMaciej W. Rozycki16-0/+215
2021-05-29MIPS/opcodes: Disassemble the RFE instructionMaciej W. Rozycki4-0/+26
2021-05-29MIPS/opcodes: Add legacy CP1 control register namesMaciej W. Rozycki9-29/+47
2021-05-29MIPS/GAS/testsuite: Add tests for coprocessor access instructionsMaciej W. Rozycki27-0/+2180
2021-05-29MIPS/opcodes: Do not use CP0 register names for control registersMaciej W. Rozycki2-4/+11
2021-05-29MIPS/opcodes: Add TX39 CP0 register namesMaciej W. Rozycki3-0/+49
2021-05-29microMIPS/opcodes: Refer FPRs rather than FCRs with DMTC1Maciej W. Rozycki7-321/+331
2021-05-29MIPS/GAS: Use FCSR rather than RA with CFC1/CTC1Maciej W. Rozycki2-4/+11
2021-05-28x86: Restore PC16 relocation overflow checkH.J. Lu4-47/+27
2021-05-27PowerPC: Add new xxmr and xxlnot extended mnemonicsPeter Bergner3-0/+13
2021-05-27nds32: __builtin_strncpy bound equals destination sizeAlan Modra2-8/+14
2021-05-26x86: Propery check PC16 reloc overflow in 16-bit mode instructionsH.J. Lu6-18/+80
2021-05-26i386: Replace movsb with movsxbSebastien Villemot2-1/+7
2021-05-26RISC-V: Allow to link the objects with unknown prefixed extensions.Nelson Chu2-0/+6
2021-05-25Arm: Fix forward thumb references [PR gas/25235]Tamar Christina4-1/+72
2021-05-24RISC-V: PR25212, Report errors for invalid march and mabi combinations.Nelson Chu27-16/+72
2021-05-22Re: Fix offset for ia64 PCREL60B relocation on HP-UXAlan Modra3-3/+17
2021-05-20Fix overflow detection in the Z80 assembler.Sergey Belyashov5-200/+227
2021-05-20PR27888, fix link of gas with zlib by libtool 2.4.6Nicolas Boulenguez3-2/+11
2021-05-19Fix offset for ia64 PCREL60B relocation on HP-UXJohn David Anglin1-1/+10
2021-05-17arm: Fix bugs with MVE vmov from two GPRs to vector lanesAlex Coplan5-3/+340
2021-05-12SAFE_BYTE_GET64Alan Modra3-3/+8
2021-05-11Report illegal Z80 load instructions.Sergey Belyashov5-0/+95
2021-05-10Add support for 8-bit and 24-bit shifts in the z80 assembler.Sergey Belyashov4-2/+35
2021-05-08support generating multi-html pages in parallelMike Frysinger3-2/+17
2021-05-08generate single html manual page by defaultMike Frysinger3-2/+9
2021-05-07Add a generic .bss directive for ELF based targets.Nick Clifton4-14/+65
2021-05-07Fix .dwsect generation for XCOFF. Handle .function generated with DWARF on X...Cl?ment Chigot11-5/+217
2021-05-07x86-64/ELF: clear src_mask for all reloc typesJan Beulich4-0/+33
2021-05-07x86: don't mix disp and imm processingJan Beulich2-1/+6
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