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2019-12-06[gas] Implement .cfi_negate_ra_state directiveKyrylo Tkachov4-0/+53
2019-12-05Arm64: simplify Crypto arch extension handlingJan Beulich2-3/+6
2019-12-05Arm64: correct "sha3" arch-extension directive handlingJan Beulich7-45/+49
2019-12-04x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifierJan Beulich9-8/+90
2019-12-04x86-64/Intel: fix CALL/JMP with dword operandJan Beulich4-6/+31
2019-12-04x86: consolidate tracking of MMX register useJan Beulich2-9/+8
2019-12-04x86/Intel: extend MOVDIRI testingJan Beulich7-0/+23
2019-12-04x86: make sure all PUSH/POP honor DefaultSizeJan Beulich4-8/+40
2019-12-04x86: drop some stray/bogus DefaultSizeJan Beulich4-9/+94
2019-11-28gas/riscv: Produce version 3 DWARF CIE by defaultAndrew Burgess6-4/+51
2019-11-28gas: Check for overflow on return column in version 1 CIE DWARFAndrew Burgess5-1/+36
2019-11-28binutils/gas/riscv: Add DWARF register numbers for CSRsAndrew Burgess4-0/+531
2019-11-28gas/riscv: Remove unneeded structureAndrew Burgess2-7/+6
2019-11-25Fix "psb CSYNC" and "bti C".Andrew Pinski7-3/+25
2019-11-25Introduce new section flag: SEC_ELF_OCTETSChristian Eggers6-11/+52
2019-11-25Reverts patches providing octet support in dwarfChristian Eggers4-63/+22
2019-11-22Arm: Change CRC from fpu feature to archititectural extensionMihail Ionescu4-16/+62
2019-11-20PR24944, gas doesn't read enough digits when parsing a floating point numberAlan Modra4-8/+23
2019-11-18gas: Add --gdwarf-cie-version command line flagAndrew Burgess13-2/+125
2019-11-14x86: fold individual Jump* attributes into a single Jump oneJan Beulich3-34/+41
2019-11-14x86: make JumpAbsolute an insn attributeJan Beulich3-21/+45
2019-11-14x86: make AnySize an insn attributeJan Beulich2-1/+5
2019-11-14x86/Intel: correct CMPSD test cases' regexp closing paren placementJan Beulich3-39/+45
2019-11-14x86/Intel: extend MOVSD/CMPSD testsuite coverageJan Beulich10-0/+386
2019-11-12RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive.Jim Wilson2-1/+5
2019-11-12[gas][arm] Enable VLDM, VSTM, VPUSH, VPOP for MVEMihail Ionescu4-44/+131
2019-11-12[binutils][arm] Update the decoding of MVE VMOV, VMVNMihail Ionescu4-2/+94
2019-11-12[gas][arm] Make .fpu reset the FPU/Coprocessor feature bitsMihail Ionescu5-2/+32
2019-11-12x86: fold EsSeg into IsStringJan Beulich2-34/+31
2019-11-12x86: eliminate ImmExt abuseJan Beulich12-352/+343
2019-11-12x86: introduce operand type "instance"Jan Beulich2-29/+55
2019-11-11Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same registerJan Beulich3-0/+10
2019-11-08i386: Only check suffix in instruction mnemonicH.J. Lu6-44/+69
2019-11-08x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich2-6/+13
2019-11-08x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich2-43/+53
2019-11-08x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich2-14/+20
2019-11-08x86: convert SReg from bitfield to enumeratorJan Beulich3-9/+18
2019-11-08x86: introduce operand type "class"Jan Beulich2-41/+73
2019-11-07[gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X]Matthew Malcomson3-0/+20
2019-11-07[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson6-5/+171
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson11-0/+330
2019-11-07[Patch][binutils][aarch64] .bfloat16 directive for AArch64 [7/10]Matthew Malcomson5-0/+98
2019-11-07[Patch][binutils][arm] .bfloat16 directive for Arm [6/X]Matthew Malcomson5-0/+96
2019-11-07[Patch][binutils] Generic support for parsing numbers in bfloat16 format [5/X]Matthew Malcomson3-29/+63
2019-11-07[binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson18-24/+807
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson10-0/+372
2019-11-07[gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson3-1/+8
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich10-55/+45
2019-11-07x86: adjust register names printed for MONITOR/MWAITJan Beulich12-201/+80
2019-11-04x86: re-arrange process_operands()Jan Beulich2-57/+54
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