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2019-06-14Regenerate with approved autotools versionAlan Modra4-22/+14
bfd/ * Makefile.in: Regenerate. * configure: Regenerate. binutils/ * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * doc/Makefile.in: Regenerate. gas/ * Makefile.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. ld/ * Makefile.in: Regenerate. * configure: Regenerate. libctf/ * configure: Regenerate.
2019-06-12Add missing ChangeLog entriesPeter Bergner1-0/+5
2019-06-12Remove the ldmx mnemonic that never made it into POWER9.Peter Bergner2-4/+0
opcodes/ * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic. gas/ * testsuite/gas/ppc/power9.d: Delete ldmx tests. * testsuite/gas/ppc/power9.s: Likewise.
2019-06-06gas: Add .enqcmd and noenqcmd directivesH.J. Lu3-0/+10
2019-06-06 Lili Cui <lili.cui@intel.com> * config/tc-i386.c (cpu_arch): Add .enqcmd. (cpu_noarch): Add noenqcmd. * doc/c-i386.texi: Document noenqcmd.
2019-06-06gas: Correct ChangeLog for commit 5d79adc4b22b0abdH.J. Lu1-12/+14
2019-06-05i386: Check vector length for EVEX vextractfXX and vinsertfXXH.J. Lu5-2/+21
Since not all vector lengths are supported by EVEX vextractfXX and vinsertfXX, decode them only with supported vector lengths. gas/ PR binutils/24633 * testsuite/gas/i386/disassem.s: Add tests for invalid vector lengths for EVEX vextractfXX and vinsertfXX. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24633 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2. (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0, EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0, EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0, EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0, EVEX_LEN_0F3A1B_P_2_W_1. * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum. (EVEX_LEN_0F3A18_P_2_W_1): Likewise. (EVEX_LEN_0F3A19_P_2_W_0): Likewise. (EVEX_LEN_0F3A19_P_2_W_1): Likewise. (EVEX_LEN_0F3A1A_P_2_W_0): Likewise. (EVEX_LEN_0F3A1A_P_2_W_1): Likewise. (EVEX_LEN_0F3A1B_P_2_W_0): Likewise. (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
2019-06-04i386: Check for reserved VEX.vvvv and EVEX.vvvvH.J. Lu5-0/+22
If VEX.vvvv and EVEX.vvvv are reserved, they must be all 1s, which are all 0s in inverted form. Add check for unused VEX.vvvv and EVEX.vvvv when disassembling VEX and EVEX instructions. gas/ PR binutils/24626 * testsuite/gas/i386/disassem.s: Add tests for reserved VEX.vvvv and EVEX.vvvv. * testsuite/gas/i386/x86-64-disassem.s: Likewise. * testsuite/gas/i386/disassem.d: Updated. * testsuite/gas/i386/x86-64-disassem.d: Likewise. opcodes/ PR binutils/24626 * i386-dis.c (print_insn): Check for unused VEX.vvvv and EVEX.vvvv when disassembling VEX and EVEX instructions. (OP_VEX): Set vex.register_specifier to 0 after readding vex.register_specifier. (OP_Vex_2src_1): Likewise. (OP_Vex_2src_2): Likewise. (OP_LWP_E): Likewise. (OP_EX_Vex): Don't check vex.register_specifier. (OP_XMM_Vex): Likewise.
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu18-1/+425
This patch enables support for VP2INTERSECT in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for VP2INTERSECT details. Make check-gas is ok. gas/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c (cpu_arch): Add .avx512_vp2intersect. (cpu_noarch): Likewise. * doc/c-i386.texi: Document avx512_vp2intersect. * testsuite/gas/i386/i386.exp: Run vp2intersect tests. * testsuite/gas/i386/vp2intersect-intel.d: New test. * testsuite/gas/i386/vp2intersect.d: Likewise. * testsuite/gas/i386/vp2intersect.s: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/vp2intersect-inval-bcast.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-intel.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.d: Likewise. * testsuite/gas/i386/x86-64-vp2intersect.s: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.l: Likewise. * testsuite/gas/i386/x86-64-vp2intersect-inval-bcast.s: Likewise. opcodes/ 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3. * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT instructions. * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS, CPU_ANY_AVX512_VP2INTERSECT_FLAGS. (cpu_flags): Add CpuAVX512_VP2INTERSECT. * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT. (i386_cpu_flags): Add cpuavx512_vp2intersect. * i386-opc.tbl: Add AVX512_VP2INTERSECT insns. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
2019-06-04Add support for Intel ENQCMD[S] instructionsH.J. Lu13-1/+183
This patch enables support for ENQCMD[S] in binutils. Please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf for ENQCMD[S] details. Make check-gas is ok. gas/ChangeLog: 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> Lili Cui <lili.cui@intel.com> * doc/c-i386.texi: Document enqcmd. * testsuite/gas/i386/enqcmd-intel.d: New file. * testsuite/gas/i386/enqcmd-inval.l: Likewise. * testsuite/gas/i386/enqcmd-inval.s: Likewise. * testsuite/gas/i386/enqcmd.d: Likewise. * testsuite/gas/i386/enqcmd.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise. * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise. * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. * testsuite/gas/i386/x86-64-enqcmd.s: Likewise. * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval, enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval, and x86-64-enqcmd. opcodes/ChangeLog: 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> Lili Cui <lili.cui@intel.com> * i386-dis.c (enum): Add MOD_0F38F8_PREFIX_1 and MOD_0F38F8_PREFIX_3. (prefix_table): New instructions (see prefix above). (mod_table): New instructions (see prefix above). * i386-gen.c (cpu_flag_init): Add entries for enqcmd. (cpu_flags): Add a bitfield for enqmcd. * i386-init.h: Regenerated. * i386-opc.h (enum): Add CpuENQCMD. (i386_cpu_flags): Add a bitfield for cpuenqcmd. * i386-opc.tbl: Add enqcmd and enqcmds instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.
2019-05-30RISC-V: Fix lui argument parsing.Jim Wilson4-5/+16
This fixes a bug reported on the riscv.org sw-dev mailing list. This rejects "lui x1,symbol", as a symbol should only be accepted here when used inside %hi(). Without the fix, this gets assembled as "lui x1,0" with no relocation which is clearly wrong. gas/ * config/tc-riscv.c (riscv_ip) <'u'>: Move O_constant check inside if statement. Delete O_symbol and O_constant check after if statement. * testsuite/gas/riscv/auipc-parsing.s: Test lui with missing %hi. * testsuite/gas/riscv/auipc-parsing.l: Update.
2019-05-28x86: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVLH.J. Lu5-0/+27
For AVX512 instructions with Disp8ShiftVL and Broadcast, we may need to add CheckRegSize to check if broadcast matches the destination register size. gas/ PR gas/24625 * testsuite/gas/i386/inval-avx512f.s: Add tests for AVX512_BF16 instructions with invalid broadcast. * testsuite/gas/i386/x86-64-inval-avx512f.s: Likewise. * testsuite/gas/i386/inval-avx512f.l: Updated. * testsuite/gas/i386/x86-64-inval-avx512f.l: Likewise. opcodes/ PR gas/24625 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVL. * i386-tbl.h: Regenerated.
2019-05-27Fix failure on powerpc 32-bit only targetsAlan Modra3-51/+140
Targets that lack ppc64 support were failing the new prefix-reloc test. This patch adds some test infrastructure to deal with that, and changes the powerpc gas usage info so that "-a64" is omitted when unsupported. I've been meaning to break up the usage message for a long time; While doing so causes translators some work now, it should make it easier next time a new powerpc option is added. * config/tc-ppc.c (is_ppc64_target): New function. (md_show_usage): Split up usage message. Don't show -a64 when unsupported. testsuite/gas/ppc/ppc.exp (supports_ppc64): New. (prefix-reloc): Only run for ppc64.
2019-05-24aarch64: override default elf .set handling in gasSzabolcs Nagy5-0/+78
Allow st_other values such as STO_AARCH64_VARIANT_PCS to be set for alias symbols independently. This is needed for ifunc symbols which are aliased to the resolver using .set and don't expect resolver attributes to override the ifunc symbol attributes. This means .variant_pcs must be added explicitly to aliases. gas/ChangeLog: * config/tc-aarch64.c (aarch64_elf_copy_symbol_attributes): Define. * config/tc-aarch64.h (aarch64_elf_copy_symbol_attributes): Declare. (OBJ_COPY_SYMBOL_ATTRIBUTES): Define. * testsuite/gas/aarch64/symbol-variant_pcs-3.d: New test. * testsuite/gas/aarch64/symbol-variant_pcs-3.s: New test.
2019-05-24aarch64: handle .variant_pcs directive in gasSzabolcs Nagy7-0/+69
In ELF objects the specified symbol is marked with STO_AARCH64_VARIANT_PCS. gas/ChangeLog: * config/tc-aarch64.c (s_variant_pcs): New function. * doc/c-aarch64.texi: Document .variant_pcs. * testsuite/gas/aarch64/symbol-variant_pcs-1.d: New test. * testsuite/gas/aarch64/symbol-variant_pcs-1.s: New test. * testsuite/gas/aarch64/symbol-variant_pcs-2.d: New test. * testsuite/gas/aarch64/symbol-variant_pcs-2.s: New test.
2019-05-24Regen POTFILES for bpfAlan Modra2-0/+6
bfd/ * po/SRC-POTFILES.in: Regenerate. gas/ * po/POTFILES.in: Regenerate. ld/ * po/BLD-POTFILES.in: Regenerate. opcodes/ * po/POTFILES.in: Regenerate.
2019-05-24PowerPC relocations for prefix insnsAlan Modra6-23/+218
include/ * elf/ppc64.h (R_PPC64_PLTSEQ_NOTOC, R_PPC64_PLTCALL_NOTOC), (R_PPC64_PCREL_OPT, R_PPC64_D34, R_PPC64_D34_LO, R_PPC64_D34_HI30), (R_PPC64_D34_HA30, R_PPC64_PCREL34, R_PPC64_GOT_PCREL34), (R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC), (R_PPC64_ADDR16_HIGHER34, R_PPC64_ADDR16_HIGHERA34), (R_PPC64_ADDR16_HIGHEST34, R_PPC64_ADDR16_HIGHESTA34), (R_PPC64_REL16_HIGHER34, R_PPC64_REL16_HIGHERA34), (R_PPC64_REL16_HIGHEST34, R_PPC64_REL16_HIGHESTA34), (R_PPC64_D28, R_PPC64_PCREL28): Define. bfd/ * reloc.c (BFD_RELOC_PPC64_D34, BFD_RELOC_PPC64_D34_LO), (BFD_RELOC_PPC64_D34_HI30, BFD_RELOC_PPC64_D34_HA30), (BFD_RELOC_PPC64_PCREL34, BFD_RELOC_PPC64_GOT_PCREL34), (BFD_RELOC_PPC64_PLT_PCREL34), (BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34), (BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34), (BFD_RELOC_PPC64_REL16_HIGHER34, BFD_RELOC_PPC64_REL16_HIGHERA34), (BFD_RELOC_PPC64_REL16_HIGHEST34, BFD_RELOC_PPC64_REL16_HIGHESTA34), (BFD_RELOC_PPC64_D28, BFD_RELOC_PPC64_PCREL28): New reloc enums. * elf64-ppc.c (PNOP): Define. (ppc64_elf_howto_raw): Add reloc howtos for new relocations. (ppc64_elf_reloc_type_lookup): Translate new bfd reloc numbers. (ppc64_elf_ha_reloc): Adjust addend for highera34 and highesta34 relocs. (ppc64_elf_prefix_reloc): New function. (struct ppc_link_hash_table): Add notoc_plt. (is_branch_reloc): Add R_PPC64_PLTCALL_NOTOC. (is_plt_seq_reloc): Add R_PPC64_PLT_PCREL34, R_PPC64_PLT_PCREL34_NOTOC, and R_PPC64_PLTSEQ_NOTOC. (ppc64_elf_check_relocs): Handle pcrel got and plt relocs. Set has_pltcall for section on seeing R_PPC64_PLTCALL_NOTOC. Handle possible need for dynamic relocs on non-pcrel powerxx relocs. (dec_dynrel_count): Handle non-pcrel powerxx relocs. (ppc64_elf_inline_plt): Handle R_PPC64_PLTCALL_NOTOC. (toc_adjusting_stub_needed): Likewise. (ppc64_elf_tls_optimize): Handle R_PPC64_PLTSEQ_NOTOC. (ppc64_elf_relocate_section): Handle new powerxx relocs. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * config/tc-ppc.c (ppc_elf_suffix): Support @pcrel, @got@pcrel, @plt@pcrel, @higher34, @highera34, @highest34, and @highesta34. (fixup_size): Handle new powerxx relocs. (md_assemble): Warn for @pcrel on non-prefix insns. Accept @l, @h and @ha on prefix insns, and infer reloc without any @ suffix. Translate powerxx relocs to suit DQ and DS field instructions. Include operand tests as well as opcode test to translate BFD_RELOC_HI16_S to BFD_RELOC_PPC_16DX_HA. (ppc_fix_adjustable): Return false for pcrel GOT and PLT relocs. (md_apply_fix): Handle new powerxx relocs. * config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): Accept BFD_RELOC_PPC64_ADDR16_HIGHER34, BFD_RELOC_PPC64_ADDR16_HIGHERA34, BFD_RELOC_PPC64_ADDR16_HIGHEST34, BFD_RELOC_PPC64_ADDR16_HIGHESTA34, BFD_RELOC_PPC64_D34, and BFD_RELOC_PPC64_D28. * testsuite/gas/ppc/prefix-reloc.d, * testsuite/gas/ppc/prefix-reloc.s: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2019-05-24PowerPC D-form prefixed loads and storesPeter Bergner6-11/+380
opcodes/ * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34), (insert_pcrel, extract_pcrel, extract_pcrel0): New functions. (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment. (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0, XTOP>): Define and add entries. (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define. (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw, pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd, plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq. gas/ * config/tc-ppc.c (ppc_insert_operand): Only sign extend fields that are 32-bits or smaller. * messages.c (as_internal_value_out_of_range): Do not truncate variables and use BFD_VMA_FMT to print them. * testsuite/gas/ppc/prefix-pcrel.s, * testsuite/gas/ppc/prefix-pcrel.d: New test. * testsuite/gas/ppc/ppc.exp: Run it.
2019-05-24PowerPC add initial -mfuture instruction supportPeter Bergner6-40/+248
This patch adds initial 64-bit insn assembler/disassembler support. The only instruction added is "pnop" along with the automatic aligning of prefix instruction so they do not cross 64-byte boundaries. include/ * dis-asm.h (WIDE_OUTPUT): Define. * opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare. (PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX), (PPC_PREFIX_P, PPC_PREFIX_SEG): Define. opcodes/ * ppc-dis.c (ppc_opts): Add "future" entry. (PREFIX_OPCD_SEGS): Define. (prefix_opcd_indices): New array. (disassemble_init_powerpc): Initialize prefix_opcd_indices. (lookup_prefix): New function. (print_insn_powerpc): Handle 64-bit prefix instructions. * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK), (PMRR, POWERXX): Define. (prefix_opcodes): New instruction table. (prefix_num_opcodes): New constant. binutils/ * objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags. gas/ * config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes. (struct insn_label_list): New. (insn_labels, free_insn_labels): New variables. (ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs. (ppc_frob_label, ppc_new_dot_label): Move functions earlier in file and call ppc_record_label. (md_assemble): Handle 64-bit prefix instructions. Align labels that are on the same line as a prefix instruction. * config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to later in the file. (md_start_line_hook): Define. (ppc_start_line_hook): Declare. * testsuite/gas/ppc/prefix-align.d, * testsuite/gas/ppc/prefix-align.s: New test. * testsuite/gas/ppc/ppc.exp: Run new test.
2019-05-23gas: add support for eBPFJose E. Marchesi41-9/+1606
This patch adds a port for the Linux kernel eBPF to the GNU assembler. A testsuite and documentation updates are included. gas/ChangeLog: 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com> * configure.ac: Handle bpf-*-* targets. * configure.tgt (generic_target): Likewise. * configure: Regenerate. * Makefile.am (TARGET_CPU_CFILES): Add tc-bpf.c. (TARGET_CPU_HFILES): Add tc-bpf.h. * Makefile.in: Regenerated. * config/tc-bpf.c: New file. * config/tc-bpf.h: Likewise. * doc/Makefile.am (CPU_DOCS): Add c-bpf.texi. * doc/Makefile.in: Regenerated. * doc/all.texi: set BPF. * doc/as.texi: Add eBPF contents. * doc/c-bpf.texi: New file. * testsuite/gas/bpf/alu.d: New file. * testsuite/gas/bpf/mem-be.d: Likewise. * testsuite/gas/bpf/mem.s: Likewise. * testsuite/gas/bpf/mem.d: Likewise. * testsuite/gas/bpf/lddw-be.d: Likewise. * testsuite/gas/bpf/lddw.s: Likewise. * testsuite/gas/bpf/lddw.d: Likewise. * testsuite/gas/bpf/jump-be.d: Likewise. * testsuite/gas/bpf/jump.s: Likewise. * testsuite/gas/bpf/jump.d: Likewise. * testsuite/gas/bpf/exit-be.d: Likewise. * testsuite/gas/bpf/exit.s: Likewise. * testsuite/gas/bpf/exit.d: Likewise. * testsuite/gas/bpf/call-be.d: Likewise. * testsuite/gas/bpf/call.s: Likewise. * testsuite/gas/bpf/call.d: Likewise. * testsuite/gas/bpf/bpf.exp: Likewise. * testsuite/gas/bpf/atomic-be.d: Likewise. * testsuite/gas/bpf/atomic.s: Likewise. * testsuite/gas/bpf/atomic.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu32.s: Likewise. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu.s: Likewise. * testsuite/gas/all/gas.exp: Introduce a nop_type for eBPF. * testsuite/gas/all/org-1.s: Support nop_type 6. * testsuite/gas/all/org-1.l: Updated to reflect changes in org-1.s.
2019-05-22S12Z: GAS: New option --mdollar-hex.John Darrington6-8/+103
This option (also implied by --traditional) causes '$' to introduce literal hexadecimal constants, rather than the modern convention '0x'. gas/ * config/tc-s12z.c (s12z_strtol): New function. (md_show_usage): Update. (md_parse_option): new case OPTION_DOLLAR_HEX. (s12z_init_after_args): (<global>): Use s12z_strtol instead of strtol. * doc/c-s12z.texi (S12Z Options): Document new option -mdollar-hex. * testsuite/gas/s12z/dollar-hex.d: New file. * testsuite/gas/s12z/dollar-hex.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-05-21[binutils, ARM] <spec_reg> changes for VMRS and VMSR instructionsSudakshina Das12-17/+193
This patch makes changes to the <spec_reg> operand for VMRS and VMSR instructions as per the Armv8.1-M Mainline. New <spec_reg> options to support are: 0b0010: FPSCR_nzcvqc, access to FPSCR condition and saturation flags. 0b1100: VPR, privileged only access to the VPR register. 0b1101: P0, access to VPR.P0 predicate fields 0b1110: FPCXT_NS, enables saving and restoring of Non-secure floating point context. 0b1111: FPCXT_S, enables saving and restoring of Secure floating point context *** gas/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (parse_operands): Update case OP_RVC to parse p0 and P0. (do_vmrs): Add checks for valid operands with respect to cpu and fpu options. (do_vmsr): Likewise. (reg_names): New reg_names for FPSCR_nzcvqc, VPR, FPCXT_NS and FPCXT_S. * testsuite/gas/arm/armv8_1-m-spec-reg.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg.s: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad1.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad2.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad3.d: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad1.l: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad2.l: New. * testsuite/gas/arm/armv8_1-m-spec-reg-bad3.l: New. * testsuite/gas/arm/vfp1xD.d: Updated to allow new valid values. * testsuite/gas/arm/vfp1xD_t2.d: Likewise. *** opcodes/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (coprocessor_opcodes): New instructions for VMRS and VMSR with the new operands.
2019-05-21[binutils, Arm] Add support for conditional instructions in Armv8.1-M MainlineSudakshina Das7-1/+162
This patch adds the following instructions which are part of the Armv8.1-M Mainline: CINC CINV CNEG CSINC CSINV CSNEG CSET CSETM CSEL gas/ChangeLog: 2019-05-21 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (TOGGLE_BIT): New. (T16_32_TAB): New entries for cinc, cinv, cneg, csinc, csinv, csneg, cset, csetm and csel. (operand_parse_code): New OP_RR_ZR. (parse_operand): Handle case for OP_RR_ZR. (do_t_cond): New. (insns): New instructions for cinc, cinv, cneg, csinc, csinv, csneg, cset, csetm, csel. * testsuite/gas/arm/armv8_1-m-cond-bad.d: New test. * testsuite/gas/arm/armv8_1-m-cond-bad.l: New test. * testsuite/gas/arm/armv8_1-m-cond-bad.s: New test. * testsuite/gas/arm/armv8_1-m-cond.d: New test. * testsuite/gas/arm/armv8_1-m-cond.s: New test. opcodes/ChangeLog: 2019-05-21 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (enum mve_instructions): New enum for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv and cneg. (mve_opcodes): New instructions as above. (is_mve_encoding_conflict): Add cases for csinc, csinv, csneg and csel. (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
2019-05-21[binutils, Arm] Add support for shift instructions in MVESudakshina Das7-0/+142
This patch adds the following instructions which are part of Armv8.1-M MVE: ASRL (imm) ASRL (reg) LSLL (imm) LSLL (reg) LSRL SQRSHRL SRQSHR SQSHLL SQSHL SRSHRL SRSHR UQRSHLL UQRSHL UQSHLL UQSHL URSHLL URSHL *** gas/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (operand_parse_code): New entries for OP_RRnpcsp_I32 (register or integer operands). (do_mve_scalar_shift): New. (insns): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshl sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr. * testsuite/gas/arm/mve-shift.d: New. * testsuite/gas/arm/mve-shift.s: New. * testsuite/gas/arm/mve-shift-bad.d: New. * testsuite/gas/arm/mve-shift-bad.s: New. * testsuite/gas/arm/mve-shift-bad.l: New. *** opcodes/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (emun mve_instructions): Updated for new instructions. (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr. (is_mve_okay_in_it): Add new instructions to TRUE list. (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15. (print_insn_mve): Updated to accept new %j, %<bitfield>m and %<bitfield>n patterns.
2019-05-21MIPS/gas: Reject $0 as source register for DAUI instructionFaraz Shahbazker4-1/+14
The MIPS64R6 TRM requires that the source register for DAUI not be r0. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS64 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 67-68. gas/ * testsuite/gas/mips/r6-branch-constraints.s: Rename to ... * testsuite/gas/mips/r6-reg-constraints.s: this and add test case for DAUI. * testsuite/gas/mips/r6-branch-constraints.l: Rename to ... * testsuite/gas/mips/r6-reg-constraints.l: this and add test for DAUI. * testsuite/gas/mips/mips.exp: Rename test from r6-branch-constraints to r6-reg-constraints. opcodes/ * mips-opc.c (mips_builtin_opcodes): Change source register constraint for DAUI.
2019-05-21[GAS, Arm] PR24559: Fix pseudo load-operations for Armv8-M BaselineAndre Vieira6-0/+53
gas/ChangeLog: 2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com> PR 24559 * config/tc-arm.c (move_or_literal_pool): Set size_req to 0 for MOVW replacement. * testsuite/gas/arm/load-pseudo.s: New test input. * testsuite/gas/arm/m0-load-pseudo.d: New test. * testsuite/gas/arm/m23-load-pseudo.d: New test. * testsuite/gas/arm/m33-load-pseudo.d: New test.
2019-05-21[binutils][Arm] Fix Branch Future relocation handling and testismsAndre Vieira9-15/+51
bfd/ChangeLog: 2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com> PR/target 24460 * elf32-arm.c (get_value_helper): Remove. (elf32_arm_final_link_relocate): Fix branch future relocations. gas/ChangeLog: 2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com> * testsuite/gas/arm/armv8_1-m-bf.d: Allow different branch target naming conventions. * testsuite/gas/arm/armv8_1-m-bfl.d: Likewise. * testsuite/gas/arm/armv8_1-m-bfcsel.d: Likewise. * testsuite/gas/arm/armv8_1-m-loloop.d: Likewise. * testsuite/gas/arm/armv8_1-m-bf-rel.d: Skip for vxworks. * testsuite/gas/arm/armv8_1-m-bf-rela.d: New test. * testsuite/gas/arm/armv8_1-m-bfl-rel.d: Skip for vxworks. * testsuite/gas/arm/armv8_1-m-bfl-rela.d: New test. ld/ChangeLog: 2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com> * testsuite/ld-arm/arm-elf.exp: Add tests * testsuite/ld-arm/bfs-0.s: New test. * testsuite/ld-arm/bfs-1.s: New test. * testsuite/ld-arm/branch-futures.d: New test.
2019-05-21GAS: Replace macro LITERAL_PREFIXDOLLAR_HEX with a runtime value.John Darrington9-13/+39
In an upcoming commit, I need to be able to set the prefix used to introduce hexadecimal literal constants using a command line flag. This is not currently possible, because the switch which determines this (LITERAL_PREFIXDOLLAR_HEX) is a macro set at build time. This change substitutes it for a variable to be set at start up. gas/ChangeLog: * expr.c (literal_prefix_dollar_hex): New variable. (operand)[case '$']: Use the new variable instead of the old macro. Also, move this instance of "case '$'" next to the other one, and enable it only in the complementary proprocessor case. * expr.h (literal_prefix_dollar_hex): Declare it. * config/tc-epiphany.c (md_begin): Assign literal_prefix_dollar_hex. * config/tc-ip2k.c: ditto * config/tc-mt.c: ditto * config/tc-epiphany.h (LITERAL_PREFIXDOLLAR_HEX): Remove macro definition. * config/tc-ip2k.h: ditto * config/tc-mt.h: ditto
2019-05-21Revert "GAS: Replace macro LITERAL_PREFIXDOLLAR_HEX with a runtime value."John Darrington8-21/+9
This reverts commit cffc205c9eaacfa312323807cd60b9d3d1c26894.
2019-05-20[MIPS] PR gas/14798: Limit IRIX5 specific default typing to IRIX targetsFaraz Shahbazker6-0/+35
On IRIX 5, every global symbol that is not explicitly labelled as being a function is assumed to be an object. There is no reason why IRIX behaviour should extend to all MIPS targets, so limit this to only IRIX targets. gas/ PR 14798 * config/tc-mips.c (s_mips_globl): Only treat symbols that are not explicitly labelled as BSF_OBJECTs for IRIX targets. * testsuite/gas/mips/pr14798.s: New test source. * testsuite/gas/mips/pr14798-irix.d: New test. * testsuite/gas/mips/pr14798.d: Likewise. * testsuite/gas/mips/mips.exp: Run the new tests. binutils/ PR 14798 * testsuite/binutils-all/readelf.ss-mips: Update reference output. * testsuite/binutils-all/readelf.ss-tmips: Likewise. ld/ PR 14798 * testsuite/ld-mips-elf/reloc-6a.s: Specify .text section for global code symbols. * testsuite/ld-mips-elf/reloc-6b.s: Likewise.
2019-05-20GAS: Replace macro LITERAL_PREFIXDOLLAR_HEX with a runtime value.John Darrington8-9/+21
In an upcoming commit, I need to be able to set the prefix used to introduce hexadecimal literal constants using a command line flag. This is not currently possible, because the switch which determines this (LITERAL_PREFIXDOLLAR_HEX) is a macro set at build time. This change substitutes it for a variable to be set at start up. gas/ChangeLog: * expr.c (literal_prefix_dollar_hex): New variable. (operand)[case '$']: Use the new variable instead of the old macro. * expr.h (literal_prefix_dollar_hex): Declare it. * config/tc-epiphany.c (md_begin): Assign literal_prefix_dollar_hex. * config/tc-ip2k.c: ditto * config/tc-mt.c: ditto * config/tc-epiphany.h (LITERAL_PREFIXDOLLAR_HEX): Remove macro definition. * config/tc-ip2k.h: ditto * config/tc-mt.h: ditto
2019-05-18S12Z (doc): Minor improvements to text and formatting.John Darrington1-53/+47
gas/ * doc/c-s12z.texi: Miscellaneous adjustments.
2019-05-17GAS (documentation): Remove trademark acknowledgements.John Darrington3-2/+7
GNU policy is not to include trademark acknowlegements in documentation [1] [1] https://www.gnu.org/prep/standards/html_node/Trademarks.html Committing as obvious. gas/ * doc/c-arm.texi (ARM Options): Remove "(r)" and "(tm)" * doc/c-bfin.texi (Blackfin Syntax): Remove "(r)"
2019-05-16[PATCH, GAS, Arm] Refactor check_simd_pred_availabilityAndre Vieira2-50/+96
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (check_simd_pred_availability): Refactor. (do_neon_dyadic_i_su): Refactor use of check_simd_pred_availability. (do_neon_dyadic_i64_su): Likewise. (do_neon_shl): Likewise. (do_neon_qshl): Likewise. (do_neon_rshl): Likewise. (do_neon_logic): Likewise. (do_neon_dyadic_if_su): Likewise. (do_neon_addsub_if_i): Likewise. (do_neon_mac_maybe_scalar): Likewise. (do_neon_fmac): Likewise. (do_neon_mul): Likewise. (do_neon_qdmulh): Likewise. (do_neon_qrdmlah): Likewise. (do_neon_abs_neg): Likewise. (do_neon_sli): Likewise. (do_neon_sri): Likewise. (do_neon_qshlu_imm): Likewise. (do_neon_cvt_1): Likewise. (do_neon_cvttb_1): Likewise. (do_neon_mvn): Likewise. (do_neon_rev): Likewise. (do_neon_dup): Likewise. (do_neon_mov): Likewise. (do_neon_rshift_round_imm): Likewise. (do_neon_sat_abs_neg): Likewise. (do_neon_cls): Likewise. (do_neon_clz): Likewise. (do_vmaxnm): Likewise. (do_vrint_1): Likewise. (do_vcmla): Likewise. (do_vcadd): Likewise.
2019-05-16[PATCH, binutils, Arm] Add Armv8.1-M Mainline and MVE enablement to NEWSAndre Vieira2-0/+7
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * NEWS: Mention Armv8.1-M Mainline and MVE. binutils/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * NEWS: Mention Armv8.1-M Mainline and MVE.
2019-05-16[PATCH 57/57][Arm][GAS] MVE TestsAndre Vieira161-0/+399210
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * testsuite/gas/arm/mve-tailpredloop.d: New test. * testsuite/gas/arm/mve-tailpredloop.s: New test. * testsuite/gas/arm/mve-vabav.d: New test. * testsuite/gas/arm/mve-vabav.s: New test. * testsuite/gas/arm/mve-vabd.d: New test. * testsuite/gas/arm/mve-vabd.s: New test. * testsuite/gas/arm/mve-vabsneg.d: New test. * testsuite/gas/arm/mve-vabsneg.s: New test. * testsuite/gas/arm/mve-vadc.d: New test. * testsuite/gas/arm/mve-vadc.s: New test. * testsuite/gas/arm/mve-vaddlv.d: New test. * testsuite/gas/arm/mve-vaddlv.s: New test. * testsuite/gas/arm/mve-vaddsub.d: New test. * testsuite/gas/arm/mve-vaddsub.s: New test. * testsuite/gas/arm/mve-vaddv.d: New test. * testsuite/gas/arm/mve-vaddv.s: New test. * testsuite/gas/arm/mve-vand.d: New test. * testsuite/gas/arm/mve-vand.s: New test. * testsuite/gas/arm/mve-vbic.d: New test. * testsuite/gas/arm/mve-vbic.s: New test. * testsuite/gas/arm/mve-vbrsr.d: New test. * testsuite/gas/arm/mve-vbrsr.s: New test. * testsuite/gas/arm/mve-vcadd.d: New test. * testsuite/gas/arm/mve-vcadd.s: New test. * testsuite/gas/arm/mve-vcls.d: New test. * testsuite/gas/arm/mve-vcls.s: New test. * testsuite/gas/arm/mve-vclz.d: New test. * testsuite/gas/arm/mve-vclz.s: New test. * testsuite/gas/arm/mve-vcmla.d: New test. * testsuite/gas/arm/mve-vcmla.s: New test. * testsuite/gas/arm/mve-vcmp.d: New test. * testsuite/gas/arm/mve-vcmp.s: New test. * testsuite/gas/arm/mve-vcmul.d: New test. * testsuite/gas/arm/mve-vcmul.s: New test. * testsuite/gas/arm/mve-vcvt-1.d: New test. * testsuite/gas/arm/mve-vcvt-1.s: New test. * testsuite/gas/arm/mve-vcvt-2.d: New test. * testsuite/gas/arm/mve-vcvt-2.s: New test. * testsuite/gas/arm/mve-vcvt-3.d: New test. * testsuite/gas/arm/mve-vcvt-3.s: New test. * testsuite/gas/arm/mve-vcvt-4.d: New test. * testsuite/gas/arm/mve-vcvt-4.s: New test. * testsuite/gas/arm/mve-vddup.d: New test. * testsuite/gas/arm/mve-vddup.s: New test. * testsuite/gas/arm/mve-vdup.d: New test. * testsuite/gas/arm/mve-vdup.s: New test. * testsuite/gas/arm/mve-veor.d: New test. * testsuite/gas/arm/mve-veor.s: New test. * testsuite/gas/arm/mve-vfma-vfms.d: New test. * testsuite/gas/arm/mve-vfma-vfms.s: New test. * testsuite/gas/arm/mve-vfmas.d: New test. * testsuite/gas/arm/mve-vfmas.s: New test. * testsuite/gas/arm/mve-vhadd-vhsub-vrhadd.d: New test. * testsuite/gas/arm/mve-vhadd-vhsub-vrhadd.s: New test. * testsuite/gas/arm/mve-vhcadd.d: New test. * testsuite/gas/arm/mve-vhcadd.s: New test. * testsuite/gas/arm/mve-vmax-vmin.d: New test. * testsuite/gas/arm/mve-vmax-vmin.s: New test. * testsuite/gas/arm/mve-vmaxa-vmina.d: New test. * testsuite/gas/arm/mve-vmaxa-vmina.s: New test. * testsuite/gas/arm/mve-vmaxnm-vminnm.d: New test. * testsuite/gas/arm/mve-vmaxnm-vminnm.s: New test. * testsuite/gas/arm/mve-vmaxnma-vminnma.s: New test. * testsuite/gas/arm/mve-vmaxnmv-vminnmv.d: New test. * testsuite/gas/arm/mve-vmaxnmv-vminnmv.s: New test. * testsuite/gas/arm/mve-vmaxv-vminv.d: New test. * testsuite/gas/arm/mve-vmaxv-vminv.s: New test. * testsuite/gas/arm/mve-vmla.d: New test. * testsuite/gas/arm/mve-vmla.s: New test. * testsuite/gas/arm/mve-vmladav.d: New test. * testsuite/gas/arm/mve-vmladav.s: New test. * testsuite/gas/arm/mve-vmlaldav.d: New test. * testsuite/gas/arm/mve-vmlaldav.s: New test. * testsuite/gas/arm/mve-vmlalv.d: New test. * testsuite/gas/arm/mve-vmlalv.s: New test. * testsuite/gas/arm/mve-vmlas.d: New test. * testsuite/gas/arm/mve-vmlas.s: New test. * testsuite/gas/arm/mve-vmlav.d: New test. * testsuite/gas/arm/mve-vmlav.s: New test. * testsuite/gas/arm/mve-vmlsdav.d: New test. * testsuite/gas/arm/mve-vmlsdav.s: New test. * testsuite/gas/arm/mve-vmlsldav.d: New test. * testsuite/gas/arm/mve-vmlsldav.s: New test. * testsuite/gas/arm/mve-vmov-1.d: New test. * testsuite/gas/arm/mve-vmov-1.s: New test. * testsuite/gas/arm/mve-vmov-2.d: New test. * testsuite/gas/arm/mve-vmov-2.s: New test. * testsuite/gas/arm/mve-vmul.d: New test. * testsuite/gas/arm/mve-vmul.s: New test. * testsuite/gas/arm/mve-vmulh.d: New test. * testsuite/gas/arm/mve-vmulh.s: New test. * testsuite/gas/arm/mve-vmullbt.d: New test. * testsuite/gas/arm/mve-vmullbt.s: New test. * testsuite/gas/arm/mve-vmvn.d: New test. * testsuite/gas/arm/mve-vmvn.s: New test. * testsuite/gas/arm/mve-vorn.d: New test. * testsuite/gas/arm/mve-vorn.s: New test. * testsuite/gas/arm/mve-vorr.d: New test. * testsuite/gas/arm/mve-vorr.s: New test. * testsuite/gas/arm/mve-vpnot.d: New test. * testsuite/gas/arm/mve-vpnot.s: New test. * testsuite/gas/arm/mve-vpsel.d: New test. * testsuite/gas/arm/mve-vpsel.s: New test. * testsuite/gas/arm/mve-vpt.d: New test. * testsuite/gas/arm/mve-vpt.s: New test. * testsuite/gas/arm/mve-vqabsneg.s: New test. * testsuite/gas/arm/mve-vqaddsub.d: New test. * testsuite/gas/arm/mve-vqaddsub.s: New test. * testsuite/gas/arm/mve-vqdmladh.d: New test. * testsuite/gas/arm/mve-vqdmladh.s: New test. * testsuite/gas/arm/mve-vqdmlah.d: New test. * testsuite/gas/arm/mve-vqdmlah.s: New test. * testsuite/gas/arm/mve-vqdmlash.d: New test. * testsuite/gas/arm/mve-vqdmlash.s: New test. * testsuite/gas/arm/mve-vqdmlsdh.d: New test. * testsuite/gas/arm/mve-vqdmlsdh.s: New test. * testsuite/gas/arm/mve-vqdmulh.d: New test. * testsuite/gas/arm/mve-vqdmulh.s: New test. * testsuite/gas/arm/mve-vqdmull.d: New test. * testsuite/gas/arm/mve-vqdmull.s: New test. * testsuite/gas/arm/mve-vqmovn.d: New test. * testsuite/gas/arm/mve-vqmovn.s: New test. * testsuite/gas/arm/mve-vqrshl.d: New test. * testsuite/gas/arm/mve-vqrshl.s: New test. * testsuite/gas/arm/mve-vqrshrn.d: New test. * testsuite/gas/arm/mve-vqrshrn.s: New test. * testsuite/gas/arm/mve-vqshl.d: New test. * testsuite/gas/arm/mve-vqshl.s: New test. * testsuite/gas/arm/mve-vrev.d: New test. * testsuite/gas/arm/mve-vrev.s: New test. * testsuite/gas/arm/mve-vrint.d: New test. * testsuite/gas/arm/mve-vrint.s: New test. * testsuite/gas/arm/mve-vrmlaldavh.d: New test. * testsuite/gas/arm/mve-vrmlaldavh.s: New test. * testsuite/gas/arm/mve-vrshl.d: New test. * testsuite/gas/arm/mve-vrshl.s: New test. * testsuite/gas/arm/mve-vsbc.d: New test. * testsuite/gas/arm/mve-vsbc.s: New test. * testsuite/gas/arm/mve-vshl.d: New test. * testsuite/gas/arm/mve-vshl.s: New test. * testsuite/gas/arm/mve-vshlc.d: New test. * testsuite/gas/arm/mve-vshlc.s: New test. * testsuite/gas/arm/mve-vshll.d: New test. * testsuite/gas/arm/mve-vshll.s: New test. * testsuite/gas/arm/mve-vshr.d: New test. * testsuite/gas/arm/mve-vshr.s: New test. * testsuite/gas/arm/mve-vshrn.d: New test. * testsuite/gas/arm/mve-vshrn.s: New test. * testsuite/gas/arm/mve-vsli.d: New test. * testsuite/gas/arm/mve-vsli.s: New test. * testsuite/gas/arm/mve-vsri.d: New test. * testsuite/gas/arm/mve-vsri.s: New test. * testsuite/gas/arm/mve-vstld.d: New test. * testsuite/gas/arm/mve-vstld.s: New test. * testsuite/gas/arm/mve-vstrldr-1.d: New test. * testsuite/gas/arm/mve-vstrldr-1.s: New test. * testsuite/gas/arm/mve-vstrldr-2.d: New test. * testsuite/gas/arm/mve-vstrldr-2.s: New test. * testsuite/gas/arm/mve-vstrldr-3.d: New test. * testsuite/gas/arm/mve-vstrldr-3.s: New test.
2019-05-16[PATCH 44/57][Arm][OBJDUMP] Add support for MVE instructions: vcvt and vrintAndre Vieira1-1/+1
opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): Add new instructions. (enum mve_unpredictable): Add new reasons. (enum mve_undefined): Likewise. (is_mve_encoding_conflict): Handle new instructions. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_undefined): Likewise. (print_mve_unpredictable): Likewise. (print_mve_rounding_mode): Likewise. (print_mve_vcvt_size): Likewise. (print_mve_size): Likewise. (print_insn_mve): Likewise.
2019-05-16[PATCH 36/57][Arm][GAS] Add support for MVE instructions: wlstp, dlstp, letp ↵Andre Vieira5-34/+152
and lctp gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (T16_32_TAB): Add new instructions. (do_t_loloop): Changed to handle tail predication variants. (md_apply_fix): Likewise. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-tailpredloop-bad.d: New test. * testsuite/gas/arm/mve-tailpredloop-bad.l: New test. * testsuite/gas/arm/mve-tailpredloop-bad.s: New test. * testsuite/gas/arm/mve-tailpredloop.d: New test.
2019-05-16[PATCH 35/57][Arm][GAS] Add support for MVE instructions: vshlc and vshllAndre Vieira8-0/+195
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_mve_vshll): New encoding function. (do_mve_vshlc): Likewise. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vshlc-bad.d: New test. * testsuite/gas/arm/mve-vshlc-bad.l: New test. * testsuite/gas/arm/mve-vshlc-bad.s: New test. * testsuite/gas/arm/mve-vshll-bad.d: New test. * testsuite/gas/arm/mve-vshll-bad.l: New test. * testsuite/gas/arm/mve-vshll-bad.s: New test.
2019-05-16[PATCH 34/57][Arm][GAS] Add support for MVE instructions: vshl and vqshlAndre Vieira8-43/+364
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): Add new operand. (parse_operands): Handle new operand. (do_neon_shl_imm): Accept MVE variants. (do_neon_shl): Likewise. (do_neon_qshl_imm): Likewise. (do_neon_qshl): Likewise. (do_neon_qshlu_imm): Likewise. (insns): Likewise. * testsuite/gas/arm/mve-vqshl-bad.d: New test. * testsuite/gas/arm/mve-vqshl-bad.l: New test. * testsuite/gas/arm/mve-vqshl-bad.s: New test. * testsuite/gas/arm/mve-vshl-bad.d: New test. * testsuite/gas/arm/mve-vshl-bad.l: New test. * testsuite/gas/arm/mve-vshl-bad.s: New test.
2019-05-16[PATCH 33/57][Arm][GAS] Add support for MVE instructions: vshr, vrshr, vsli, ↵Andre Vieira14-16/+343
vsri, vrev16, vrev32 and vrev64 gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_neon_sli): Accept MVE variants. (do_neon_sri): Likewise. (do_neon_rev): Likewise. (do_neon_rshift_round_imm): Likewise. (insns): Likewise. * testsuite/gas/arm/mve-vrev-bad.d: New test. * testsuite/gas/arm/mve-vrev-bad.l: New test. * testsuite/gas/arm/mve-vrev-bad.s: New test. * testsuite/gas/arm/mve-vshr-bad.d: New test. * testsuite/gas/arm/mve-vshr-bad.l: New test. * testsuite/gas/arm/mve-vshr-bad.s: New test. * testsuite/gas/arm/mve-vsli-bad.d: New test. * testsuite/gas/arm/mve-vsli-bad.l: New test. * testsuite/gas/arm/mve-vsli-bad.s: New test. * testsuite/gas/arm/mve-vsri-bad.d: New test. * testsuite/gas/arm/mve-vsri-bad.l: New test. * testsuite/gas/arm/mve-vsri-bad.s: New test.
2019-05-16[PATCH 32/57][Arm][GAS] Add support for MVE instructions: vrintn, vrintx, ↵Andre Vieira5-10/+127
vrinta, vrintz, vrintm and vrintp gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_vrint_1): Accept MVE variants. (insns): Change entries to accept MVE variants. * testsuite/gas/arm/mve-vrint-bad.d: New test. * testsuite/gas/arm/mve-vrint-bad.l: New test. * testsuite/gas/arm/mve-vrint-bad.s: New test.
2019-05-16[PATCH 31/57][Arm][GAS] Add support for MVE instructions: vshrn[tb], ↵Andre Vieira8-0/+358
vrshrn[tb], vqshrn[tb], vqshrun[tb], vqrshrn[tb] and vqrshrun[tb] gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (M_MNEM_vshrnt, M_MNEM_vshrnb, M_MNEM_vrshrnt, M_MNEM_vqshrnt, M_MNEM_vqshrnb, M_MNEM_vqshrunt, M_MNEM_vqshrunb, M_MNEM_vrshrnb, M_MNEM_vqrshrnt, M_MNEM_vqrshrnb, M_MNEM_vqrshrunt, M_MNEM_vqrshrunb): New instruction encodings. (do_mve_vshrn): New encoding function. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vqrshrn-bad.d: New test. * testsuite/gas/arm/mve-vqrshrn-bad.l: New test. * testsuite/gas/arm/mve-vqrshrn-bad.s: New test. * testsuite/gas/arm/mve-vshrn-bad.d: New test. * testsuite/gas/arm/mve-vshrn-bad.l: New test. * testsuite/gas/arm/mve-vshrn-bad.s: New test.
2019-05-16[PATCH 30/57][Arm][GAS] Add support for MVE instructions: vqmovnt, vqmovnb, ↵Andre Vieira11-9/+366
vqmovunt, vqmovunb, vqrshl and vrshl gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (M_MNEM_vqmovnt, M_MNEM_vqmovnb, M_MNEM_vqmovunt, M_MNEM_vqmovunb): New instruction encodings. (do_mve_vqmovn): New encoding function. (do_neon_rshl): Change to accepte MVE variants. (insns): Change entries and add new for MVE mnemonics. * testsuite/gas/arm/mve-vqmovn-bad.d: New test. * testsuite/gas/arm/mve-vqmovn-bad.l: New test. * testsuite/gas/arm/mve-vqmovn-bad.s: New test. * testsuite/gas/arm/mve-vqrshl-bad.d: New test. * testsuite/gas/arm/mve-vqrshl-bad.l: New test. * testsuite/gas/arm/mve-vqrshl-bad.s: New test. * testsuite/gas/arm/mve-vrshl-bad.d: New test. * testsuite/gas/arm/mve-vrshl-bad.l: New test. * testsuite/gas/arm/mve-vrshl-bad.s: New test.
2019-05-16[PATCH 29/57][Arm][GAS] Add support for MVE instructions: vqdmullt and vqdmullbAndre Vieira5-0/+167
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): Add new operand. (parse_operands): Handle new operand. (do_mve_vqdmull): New encoding function. (insns): Add entry for MVE mnemonics. * testsuite/gas/arm/mve-vqdmull-bad.d: New test. * testsuite/gas/arm/mve-vqdmull-bad.l: New test. * testsuite/gas/arm/mve-vqdmull-bad.s: New test.
2019-05-16[PATCH 28/57][Arm][GAS] Add support for MVE instructions: vqdmlah, vqrdmlah, ↵Andre Vieira5-29/+229
vqdmlash, vqrdmlash, vqdmulh and vqrdmulh gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): Add new operand. (parse_operands): Handle new operand. (mve_encode_qqr): Handle new instructions. (do_neon_qdmulh): Add support for MVE variants. (do_neon_qrdmlah): Likewise. (do_mve_vqdmlah): New encoding function. (insns): Change entries and add new entries for MVE mnemonics. * testsuite/gas/arm/mve-vqdmulh-bad.d: New test. * testsuite/gas/arm/mve-vqdmulh-bad.l: New test. * testsuite/gas/arm/mve-vqdmulh-bad.s: New test.
2019-05-16[PATCH 27/57][Arm][GAS] Add support for MVE instructions: vqdmladh, ↵Andre Vieira8-0/+296
vqrdmladh, vqdmlsdh and vqrdmlsdh gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_mve_vqdmladh): New encoding function. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vqdmladh-bad.d: New test. * testsuite/gas/arm/mve-vqdmladh-bad.l: New test. * testsuite/gas/arm/mve-vqdmladh-bad.s: New test. * testsuite/gas/arm/mve-vqdmlsdh-bad.d: New test. * testsuite/gas/arm/mve-vqdmlsdh-bad.l: New test. * testsuite/gas/arm/mve-vqdmlsdh-bad.s: New test.
2019-05-16[PATCH 26/57][Arm][GAS] Add support for MVE instructions: vpnot and vpselAndre Vieira8-0/+113
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_mve_vpsel): New encoding function. (do_mve_vpnot): Likewise. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vpnot-bad.d: New test. * testsuite/gas/arm/mve-vpnot-bad.l: New test. * testsuite/gas/arm/mve-vpnot-bad.s: New test. * testsuite/gas/arm/mve-vpsel-bad.d: New test. * testsuite/gas/arm/mve-vpsel-bad.l: New test. * testsuite/gas/arm/mve-vpsel-bad.s: New test.
2019-05-16[PATCH 25/57][Arm][GAS] Add support for MVE instruction: vmvn, vqabs and vqnegAndre Vieira8-5/+145
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_neon_mvn): Change to accept MVE variants. (do_neon_sat_abs_neg): Likewise. (insns): Likewise. * testsuite/gas/arm/mve-vmvn-bad.d: New test. * testsuite/gas/arm/mve-vmvn-bad.l: New test. * testsuite/gas/arm/mve-vmvn-bad.s: New test. * testsuite/gas/arm/mve-vqabsneg-bad.d: New test. * testsuite/gas/arm/mve-vqabsneg-bad.l: New test. * testsuite/gas/arm/mve-vqabsneg-bad.s: New test.
2019-05-16[PATCH 24/57][Arm][GAS] Add support for MVE instructions: vmlas, vmulh and ↵Andre Vieira8-0/+168
vrmulh gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_mve_vmlas): New encoding function. (do_mve_vmulh): Likewise. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vmlas-bad.d: New test. * testsuite/gas/arm/mve-vmlas-bad.l: New test. * testsuite/gas/arm/mve-vmlas-bad.s: New test. * testsuite/gas/arm/mve-vmulh-bad.d: New test. * testsuite/gas/arm/mve-vmulh-bad.l: New test. * testsuite/gas/arm/mve-vmulh-bad.s: New test.
2019-05-16[PATCH 23/57][Arm][GAS] Add support for MVE instructions: vmla, vmul, vqadd ↵Andre Vieira14-13/+431
and vqsub gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): New operand. (parse_operands): Handle new operand. (mve_encode_qqr): Handle new instructions. (do_neon_dyadic_i64_su): Accept MVE variants. (neon_dyadic_misc): Likewise. (do_neon_mac_maybe_scalar): Likewise. (do_neon_mul): Likewise. (insns): Change to accept MVE variants. * testsuite/gas/arm/mve-vmla-bad.d: New test. * testsuite/gas/arm/mve-vmla-bad.l: New test. * testsuite/gas/arm/mve-vmla-bad.s: New test. * testsuite/gas/arm/mve-vmul-bad-1.d: New test. * testsuite/gas/arm/mve-vmul-bad-1.l: New test. * testsuite/gas/arm/mve-vmul-bad-1.s: New test. * testsuite/gas/arm/mve-vmul-bad-2.d: New test. * testsuite/gas/arm/mve-vmul-bad-2.l: New test. * testsuite/gas/arm/mve-vmul-bad-2.s: New test. * testsuite/gas/arm/mve-vqaddsub-bad.d: New test. * testsuite/gas/arm/mve-vqaddsub-bad.l: New test. * testsuite/gas/arm/mve-vqaddsub-bad.s: New test.
generated by cgit v1.1 at 2024-10-15 09:18:01 +0000