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2023-07-04x86: flag EVEX.z set when destination is a mask registerJan Beulich2-0/+4
While only zeroing-masking is possible in this case, this still requires EVEX.z to be clear. Introduce a "global" flag right here, to be re-used by checks which need to live in specific operand handlers.
2023-07-04x86: re-work EVEX-z-without-masking checkJan Beulich1-2/+1
Rather than corrupting disassmbly altogether, flag EVEX.z set as bad when masking isn't in effect in the first place at the time the destination operand is actually processed.
2023-07-04Updated Ukranian, Romanian and German translations for various sub-directoriesNick Clifton1-2537/+2826
2023-07-04arc: Update default target CPU to match GCC defaultsClaudiu Zissulescu1-1/+1
Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2023-07-03IBM Z: Fix pcrel relocs for symA-symB expressionsAndreas Krebbel2-5/+11
The code in md_apply_fix which tries to deduce from the operand type which reloc to apply currently does the wrong thing for absolute relocs which have been re-written by fixup_segment as pc-relative to implement a subtraction of a local and an external symbol. In all these cases we wrongly emit an absolute reloc because we ignore the fx_pcrel flag in md_apply_fix. However, only for the last one we actually support a pc relative relocation of the proper size and can implement it accordingly. For the other 3 we have to issue an error. foo: cli 0(%r2),undef-foo la %r2,undef-foo(%r2) lay %r2,undef-foo(%r2) lhi %r2,undef-foo
2023-07-03Change version number to 2.41.50 and regenerate filesNick Clifton3-2493/+2681
2023-07-03Add markers for the 2.41 branchNick Clifton2-0/+6
2023-07-03gas: NEWS: Announce LoongArch changes in the 2.41 cycleWANG Xuerui1-0/+12
gas/ChangeLog: * NEWS: Mention LoongArch changes for 2.41. Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-07-03LoongArch: gas: Fix shared buildsWANG Xuerui1-1/+0
Formerly an include of libbfd.h was added in commit 56576f4a722 ("LoongArch: gas: Add support for linker relaxation."), in order to allow calling _bfd_read_unsigned_leb128 from gas, but doing so broke shared builds. Commit d2fddb6d783 fixed this reference but did not remove the now unnecessary inclusion of libbfd.h. The gas_assert macro expands into a conditional call to abort(), but "abort" is re-defined to _bfd_abort in libbfd.h, so the extra include breaks any gas_assert usage, and should be removed. gas/ChangeLog: * config/tc-loongarch.c: Don't include libbfd.h. Fixes: d2fddb6d783 ("LoongArch: Fix ld "undefined reference" error with --enable-shared") Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-07-01RISC-V: Add support for the Zvksc ISA extensionNathan Huckleberry2-0/+28
Zvksc is part of the vector crypto extensions. Zvksc is shorthand for the following set of extensions: - Zvks - Zvbc bfd/ChangeLog: * elfxx-riscv.c: Define Zvksc extension. gas/ChangeLog: * testsuite/gas/riscv/zvksc.d: New test. * testsuite/gas/riscv/zvksc.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvknc ISA extensionNathan Huckleberry2-0/+28
Zvknc is part of the vector crypto extensions. Zvknc is shorthand for the following set of extensxions: - Zvkn - Zvbc bfd/ChangeLog: * elfxx-riscv.c: Define Zvknc extension. gas/ChangeLog: * testsuite/gas/riscv/zvknc.d: New test. * testsuite/gas/riscv/zvknc.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvksg ISA extensionNathan Huckleberry2-0/+16
Zvksg is part of the vector crypto extensions. Zvksg is shorthand for the following set of extensions: - Zvks - Zvkg bfd/ChangeLog: * elfxx-riscv.c: Define Zvksg extension. gas/ChangeLog: * testsuite/gas/riscv/zvksg.d: New test. * testsuite/gas/riscv/zvksg.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvks ISA extensionChristoph Müllner2-0/+81
Zvks is part of the vector crypto extensions. Zvks is shorthand for the following set of extensions: - Zvksed - Zvksh - Zvbb - Zvkt bfd/ChangeLog: * elfxx-riscv.c: Define Zvks extension. gas/ChangeLog: * testsuite/gas/riscv/zvks.d: New test. * testsuite/gas/riscv/zvks.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvkng ISA extensionNathan Huckleberry2-0/+16
Zvkng is part of the vector crypto extensions. Zvkng is shorthand for the following set of extensions: - Zvkn - Zvkg bfd/ChangeLog: * elfxx-riscv.c: Define Zvkng extension. gas/ChangeLog: * testsuite/gas/riscv/zvkng.d: New test. * testsuite/gas/riscv/zvkng.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvkn ISA extensionChristoph Müllner2-0/+81
Zvkn is part of the vector crypto extensions. Zvkn is shorthand for the following set of extensions: - Zvkned - Zvknhb - Zvbb - Zvkt bfd/ChangeLog: * elfxx-riscv.c: Define Zvkn extension. gas/ChangeLog: * testsuite/gas/riscv/zvkn.d: New test. * testsuite/gas/riscv/zvkn.s: New test. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvksh ISA extensionChristoph Müllner2-0/+14
Zvksh is part of the vector crypto extensions. This extension adds the following instructions: - vsm3me.vv - vsm3c.vi bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvksh. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvksh.d: New test. * testsuite/gas/riscv/zvksh.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VSM3C_VI): New. (MASK_VSM3C_VI): New. (MATCH_VSM3ME_VV): New. (MASK_VSM3ME_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvksh. opcodes/ChangeLog: * riscv-opc.c: Add Zvksh instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvksed ISA extensionChristoph Müllner2-0/+16
Zvksed is part of the vector crypto extensions. This extension adds the following instructions: - vsm4k.vi - vsm4r.[vv,vs] bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvksed. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvksed.d: New test. * testsuite/gas/riscv/zvksed.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VSM4K_VI): New. (MASK_VSM4K_VI): New. (MATCH_VSM4R_VS): New. (MASK_VSM4R_VS): New. (MATCH_VSM4R_VV): New. (MASK_VSM4R_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvksed. opcodes/ChangeLog: * riscv-opc.c: Add Zvksed instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvknh[a,b] ISA extensionsChristoph Müllner3-0/+27
Zvknh[a,b] are parts of the vector crypto extensions. This extension adds the following instructions: - vsha2ms.vv - vsha2c[hl].vv bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvknh[a,b]. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvknha.d: New test. * testsuite/gas/riscv/zvknha_zvknhb.s: New test. * testsuite/gas/riscv/zvknhb.d: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VSHA2CH_VV): New. (MASK_VSHA2CH_VV): New. (MATCH_VSHA2CL_VV): New. (MASK_VSHA2CL_VV): New. (MATCH_VSHA2MS_VV): New. (MASK_VSHA2MS_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvknh[a,b]. opcodes/ChangeLog: * riscv-opc.c: Add Zvknh[a,b] instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvkned ISA extensionChristoph Müllner2-0/+34
Zvkned is part of the vector crypto extensions. This extension adds the following instructions: - vaesef.[vv,vs] - vaesem.[vv,vs] - vaesdf.[vv,vs] - vaesdm.[vv,vs] - vaeskf1.vi - vaeskf2.vi - vaesz.vs bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvkned. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvkned.d: New test. * testsuite/gas/riscv/zvkned.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VAESDF_VS): New. (MASK_VAESDF_VS): New. (MATCH_VAESDF_VV): New. (MASK_VAESDF_VV): New. (MATCH_VAESDM_VS): New. (MASK_VAESDM_VS): New. (MATCH_VAESDM_VV): New. (MASK_VAESDM_VV): New. (MATCH_VAESEF_VS): New. (MASK_VAESEF_VS): New. (MATCH_VAESEF_VV): New. (MASK_VAESEF_VV): New. (MATCH_VAESEM_VS): New. (MASK_VAESEM_VS): New. (MATCH_VAESEM_VV): New. (MASK_VAESEM_VV): New. (MATCH_VAESKF1_VI): New. (MASK_VAESKF1_VI): New. (MATCH_VAESKF2_VI): New. (MASK_VAESKF2_VI): New. (MATCH_VAESZ_VS): New. (MASK_VAESZ_VS): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvkned. opcodes/ChangeLog: * riscv-opc.c: Add Zvkned instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvkg ISA extensionChristoph Müllner2-0/+12
Zvkg is part of the vector crypto extensions. This extension adds the following instructions: - vghsh.vv - vgmul.vv bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvkg. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvkg.d: New test. * testsuite/gas/riscv/zvkg.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VGHSH_VV): New. (MASK_VGHSH_VV): New. (MATCH_VGMUL_VV): New. (MASK_VGMUL_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvkg. opcodes/ChangeLog: * riscv-opc.c: Add Zvkg instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvbc extensionNathan Huckleberry2-0/+24
Zvbc is part of the crypto vector extensions. This extension adds the following instructions: - vclmul.[vv,vx] - vclmulh.[vv,vx] bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvbc. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvbc.d: New test. * testsuite/gas/riscv/zvbc.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VCLMUL_VV): New. (MASK_VCLMUL_VV): New. (MATCH_VCLMUL_VX): New. (MASK_VCLMUL_VX): New. (MATCH_VCLMULH_VV): New. (MASK_VCLMULH_VV): New. (MATCH_VCLMULH_VX): New. (MASK_VCLMULH_VX): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvbc. opcodes/ChangeLog: * riscv-opc.c: Add Zvbc instruction. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01RISC-V: Add support for the Zvbb ISA extensionChristoph Müllner3-0/+90
Zvbb is part of the vector crypto extensions. This extension adds the following instructions: - vandn.[vv,vx] - vbrev.v - vbrev8.v - vrev8.v - vclz.v - vctz.v - vcpop.v - vrol.[vv,vx] - vror.[vv,vx,vi] - vwsll.[vv,vx,vi] bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvbb. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add 'l' as new format string directive. (riscv_ip): Likewise. * testsuite/gas/riscv/zvbb.d: New test. * testsuite/gas/riscv/zvbb.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VANDN_VV): New. (MASK_VANDN_VV): New. (MATCH_VANDN_VX): New. (MASK_VANDN_VX): New. (MATCH_VBREV8_V): New. (MASK_VBREV8_V): New. (MATCH_VBREV_V): New. (MASK_VBREV_V): New. (MATCH_VCLZ_V): New. (MASK_VCLZ_V): New. (MATCH_VCPOP_V): New. (MASK_VCPOP_V): New. (MATCH_VCTZ_V): New. (MASK_VCTZ_V): New. (MATCH_VREV8_V): New. (MASK_VREV8_V): New. (MATCH_VROL_VV): New. (MASK_VROL_VV): New. (MATCH_VROL_VX): New. (MASK_VROL_VX): New. (MATCH_VROR_VI): New. (MASK_VROR_VI): New. (MATCH_VROR_VV): New. (MASK_VROR_VV): New. (MATCH_VROR_VX): New. (MASK_VROR_VX): New. (MATCH_VWSLL_VI): New. (MASK_VWSLL_VI): New. (MATCH_VWSLL_VV): New. (MASK_VWSLL_VV): New. (MATCH_VWSLL_VX): New. (MASK_VWSLL_VX): New. (DECLARE_INSN): New. * opcode/riscv.h (EXTRACT_RVV_VI_UIMM6): New. (ENCODE_RVV_VI_UIMM6): New. (enum riscv_insn_class): Add instruction class for Zvbb. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add 'l' as new format string directive. * riscv-opc.c: Add Zvbb instructions. Signed-off-by: Nathan Huckleberry <nhuck@google.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-06-30RISC-V: Add support for the Zfa extensionChristoph Müllner11-0/+326
This patch adds support for the RISC-V Zfa extension, which introduces additional floating-point instructions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (Modular Convert-to-Integer) * fmv* to access high bits of FP registers in case XLEN < FLEN * fleq/fltq (quiet comparison instructions) Zfa defines its instructions in combination with the following extensions: * single-precision floating-point (F) * double-precision floating-point (D) * quad-precision floating-point (Q) * half-precision floating-point (Zfh) This patch is based on an earlier version from Tsukasa OI: https://sourceware.org/pipermail/binutils/2022-September/122939.html Most significant change to that commit is the switch from the rs1-field value to the actual floating-point value in the last operand of the fli* instructions. Everything that strtof() can parse is accepted and the '%a' printf specifier is used to output hex floating-point literals in the disassembly. The Zfa specification is frozen (and has passed public review). It is available as a chapter in "The RISC-V Instruction Set Manual: Volume 1": https://github.com/riscv/riscv-isa-manual/releases bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for 'Zfa' extension. (riscv_multi_subset_supports_ext): Likewise. (riscv_implicit_subsets): Add 'Zfa' -> 'F' dependency. gas/ChangeLog: * config/tc-riscv.c (flt_lookup): New helper to lookup a float value in an array. (validate_riscv_insn): Add 'Wfv' as new format string directive. (riscv_ip): Likewise. * doc/c-riscv.texi: Add floating-point chapter and describe limiations of the Zfa FP literal parsing. * testsuite/gas/riscv/zfa-32.d: New test. * testsuite/gas/riscv/zfa-32.s: New test. * testsuite/gas/riscv/zfa-64.d: New test. * testsuite/gas/riscv/zfa-64.s: New test. * testsuite/gas/riscv/zfa-fail.d: New test. * testsuite/gas/riscv/zfa-fail.l: New test. * testsuite/gas/riscv/zfa-fail.s: New test. * testsuite/gas/riscv/zfa.d: New test. * testsuite/gas/riscv/zfa.s: New test. * testsuite/gas/riscv/zfa.s: New test. * opcode/riscv-opc.h (MATCH_FLI_H): New. (MASK_FLI_H): New. (MATCH_FMINM_H): New. (MASK_FMINM_H): New. (MATCH_FMAXM_H): New. (MASK_FMAXM_H): New. (MATCH_FROUND_H): New. (MASK_FROUND_H): New. (MATCH_FROUNDNX_H): New. (MASK_FROUNDNX_H): New. (MATCH_FLTQ_H): New. (MASK_FLTQ_H): New. (MATCH_FLEQ_H): New. (MASK_FLEQ_H): New. (MATCH_FLI_S): New. (MASK_FLI_S): New. (MATCH_FMINM_S): New. (MASK_FMINM_S): New. (MATCH_FMAXM_S): New. (MASK_FMAXM_S): New. (MATCH_FROUND_S): New. (MASK_FROUND_S): New. (MATCH_FROUNDNX_S): New. (MASK_FROUNDNX_S): New. (MATCH_FLTQ_S): New. (MASK_FLTQ_S): New. (MATCH_FLEQ_S): New. (MASK_FLEQ_S): New. (MATCH_FLI_D): New. (MASK_FLI_D): New. (MATCH_FMINM_D): New. (MASK_FMINM_D): New. (MATCH_FMAXM_D): New. (MASK_FMAXM_D): New. (MATCH_FROUND_D): New. (MASK_FROUND_D): New. (MATCH_FROUNDNX_D): New. (MASK_FROUNDNX_D): New. (MATCH_FLTQ_D): New. (MASK_FLTQ_D): New. (MATCH_FLEQ_D): New. (MASK_FLEQ_D): New. (MATCH_FLI_Q): New. (MASK_FLI_Q): New. (MATCH_FMINM_Q): New. (MASK_FMINM_Q): New. (MATCH_FMAXM_Q): New. (MASK_FMAXM_Q): New. (MATCH_FROUND_Q): New. (MASK_FROUND_Q): New. (MATCH_FROUNDNX_Q): New. (MASK_FROUNDNX_Q): New. (MATCH_FLTQ_Q): New. (MASK_FLTQ_Q): New. (MATCH_FLEQ_Q): New. (MASK_FLEQ_Q): New. (MATCH_FCVTMOD_W_D): New. (MASK_FCVTMOD_W_D): New. (MATCH_FMVH_X_D): New. (MASK_FMVH_X_D): New. (MATCH_FMVH_X_Q): New. (MASK_FMVH_X_Q): New. (MATCH_FMVP_D_X): New. (MASK_FMVP_D_X): New. (MATCH_FMVP_Q_X): New. (MASK_FMVP_Q_X): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction classes for the Zfa extension. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add support for new format string directive 'Wfv'. * riscv-opc.c: Add Zfa instructions. Co-Developed-by: Tsukasa OI <research_trasio@irq.a4lg.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Co-Developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-06-30LoongArch: gas: Add LVZ and LBT instructions supportmengqinggang4-26/+402
gas/ChangeLog: * config/tc-loongarch.c (md_parse_option): Add LARCH_opts.ase_lvz and LARCH_opts.ase_lbt. * testsuite/gas/loongarch/uleb128.d: Regenerated. * testsuite/gas/loongarch/lvz-lbt.d: New test. * testsuite/gas/loongarch/lvz-lbt.s: New test. include/ChangeLog: * opcode/loongarch.h (ase_lvz): New. (ase_lbt): New. opcodes/ChangeLog: * loongarch-dis.c (set_default_loongarch_dis_options): Add LARCH_opts.ase_lvz and LARCH_opts.ase_lbt. * loongarch-opc.c (struct loongarch_ase): Add LVZ and LBT instructions.
2023-06-30LoongArch: Deprecate $v[01], $fv[01] and $x names per specWANG Xuerui4-5/+67
As outlined in the LoongArch ELF psABI spec [1], it is actually already 2 versions after the initial LoongArch support, and the $v[01] and $fv[01] names should really get sunset by now. In addition, the "$x" name for $r21 was never included in any released version of the ABI spec, and such usages are all fixed to say just $r21 for every project I could think of that accepted a LoongArch port. Plus, the upcoming LSX/LASX support makes use of registers named "$vrNN" and "$xrNN", so having "$vN" and "$x" alongside would almost certainly create confusion for developers. Issue warnings for such usages per the deprecation procedure detailed in the spec, so we can finally remove support in the next release cycle after this. [1]: https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html gas/ChangeLog: * config/tc-loongarch.c: Init canonical register ABI name mappings and deprecated register names. (loongarch_args_parser_can_match_arg_helper): Warn in case of deprecated register name usage. * testsuite/gas/loongarch/deprecated_reg_aliases.d: New test. * testsuite/gas/loongarch/deprecated_reg_aliases.l: Likewise. * testsuite/gas/loongarch/deprecated_reg_aliases.s: Likewise. include/ChangeLog: * opcode/loongarch.h: Rename global variables. opcodes/ChangeLog: * loongarch-opc.c: Rename the alternate/deprecated register name mappings, and move $x to the deprecated name map. Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-06-30opcodes/loongarch: print unrecognized insn words with the .word directiveWANG Xuerui3-10/+28
For better round-trip fidelity and readability in general. gas/ChangeLog: * testsuite/gas/loongarch/uleb128.d: Update test case. * testsuite/gas/loongarch/raw-insn.d: New test. * testsuite/gas/loongarch/raw-insn.s: Likewise. opcodes/ChangeLog: * loongarch-dis.c (disassemble_one): Print ".word" if !opc. Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-06-30opcodes/loongarch: do not print hex notation for signed immediatesWANG Xuerui10-227/+227
The additional hex notation was minimally useful when one had to inspect code with heavy bit manipulation, or of unclear signedness, but it clutters the output, and the style is not regular assembly language syntax either. Precisely how one approaches the original use case is not taken care of in this patch (maybe we want a disassembler option forcing a certain style for immediates, like for example printing every immediate in decimal or hexadecimal notation), but at least let's stop the current practice. ChangeLog: * testsuite/gas/loongarch/imm_ins.d: Update test case. * testsuite/gas/loongarch/imm_ins_32.d: Likewise. * testsuite/gas/loongarch/imm_op.d: Likewise. * testsuite/gas/loongarch/jmp_op.d: Likewise. * testsuite/gas/loongarch/load_store_op.d: Likewise. * testsuite/gas/loongarch/macro_op.d: Likewise. * testsuite/gas/loongarch/macro_op_32.d: Likewise. * testsuite/gas/loongarch/privilege_op.d: Likewise. * testsuite/gas/loongarch/uleb128.d: Likewise. * testsuite/gas/loongarch/vector.d: Likewise. ld/ChangeLog: * testsuite/ld-loongarch-elf/jmp_op.d: Update test case. * testsuite/ld-loongarch-elf/macro_op.d: Likewise. * testsuite/ld-loongarch-elf/macro_op_32.d: Likewise. opcodes/ChangeLog: * loongarch-dis.c (dis_one_arg): Remove the "(0x%x)" part from disassembly output of signed immediate operands. Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-06-30LoongArch: support disassembling certain pseudo-instructionsWANG Xuerui13-36/+37
Add a flag in the pinfo field for being able to mark certain specialized matchers as disassembler-only, so some degree of isolation between assembler-side and disassembler-side can be achieved. This isolation is necessary, firstly because some pseudo-instructions cannot be fully described in the opcode table, like `li.[wd]`, so the corresponding opcode entry cannot have meaningful match/mask values. Secondly, some of these pseudo-instructions can be realized in more than one plausible ways; e.g. `li.w rd, <something between 0 and 0x7ff>` can be realized on LA64 with any of `addi.w`, `addi.d` or `ori`. If we tie disassembly of such aliases with the corresponding GAS support, only one canonical form among the above would be recognized as `li.w`, and it would mildly impact the readability of disassembly output. People wanting the exact disassembly can always set `-M no-aliases` to get the original behavior back. In addition, in certain cases, information is irreversibly lost after assembling, so perfect round-trip would not be possible in such cases. For example, `li.w` and `li.d` of immediates within int32_t range produce the same code; in this patch, `addi.d rd, $zero, imm` is treated as `li.d`, while `addi.w` and `ori` immediate loads are shown as `li.w`, due to the expressible value range well within 32 bits. gas/ChangeLog: * config/tc-loongarch.c (get_loongarch_opcode): Ignore disassembler-only aliases. * testsuite/gas/loongarch/64_pcrel.d: Update test case. * testsuite/gas/loongarch/imm_ins.d: Likewise. * testsuite/gas/loongarch/imm_ins_32.d: Likewise. * testsuite/gas/loongarch/jmp_op.d: Likewise. * testsuite/gas/loongarch/li.d: Likewise. * testsuite/gas/loongarch/macro_op.d: Likewise. * testsuite/gas/loongarch/macro_op_32.d: Likewise. * testsuite/gas/loongarch/macro_op_large_abs.d: Likewise. * testsuite/gas/loongarch/macro_op_large_pc.d: Likewise. * testsuite/gas/loongarch/nop.d: Likewise. * testsuite/gas/loongarch/relax_align.d: Likewise. * testsuite/gas/loongarch/reloc.d: Likewise. include/ChangeLog: * opcode/loongarch.h (INSN_DIS_ALIAS): Add. ld/ChangeLog: * testsuite/ld-loongarch-elf/jmp_op.d: Update test case. * testsuite/ld-loongarch-elf/macro_op.d: Likewise. * testsuite/ld-loongarch-elf/macro_op_32.d: Likewise. * testsuite/ld-loongarch-elf/relax-align.dd: Likewise. opcodes/ChangeLog: * loongarch-dis.c: Move register name map declarations to top. (get_loongarch_opcode_by_binfmt): Consider aliases when disassembling without the no-aliases option. (parse_loongarch_dis_option): Support the no-aliases option. * loongarch-opc.c: Collect pseudo instructions into a new dedicated table. Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-06-29sframe: bfd: gas: ld: format bump to SFrame version 2Indu Bhagat16-17/+22
SFrame version 2 encodes the size of repetitive insn block explicitly in the format. Add information in the SFrame FDE to convey the size of the block of repeating instructions. This information is used only for SFrame FDEs of type SFRAME_FDE_TYPE_PCMASK. Introduce two extra bytes for padding: this ensures that the memory accesses to the members of the SFrame Frame Descriptor Entry (FDE) are naturally aligned. gas generates SFrame section with version SFRAME_VERSION_2 by default. libsframe provides two new APIs to: - get an SFrame FDE data from the decoder context, and - add an SFrame FDE to the encoder context. The additional argument (for rep_block_size) is useful for SFrame FDEs where FDE type is SFRAME_FDE_TYPE_PCMASK. The linker will generate the output SFrame sections in the SFRAME_VERSION_2 format. If the input sections offered to the linker are not all in the SFRAME_VERSION_2 format, the linker issues an error to the user. objdump/readelf will show the following message to the user if .sframe section in SFRAME_VERSION_1 format is seen: "No further information can be displayed. SFrame version not supported." In other words, like the rest of the binutils, only the current SFrame format version, i.e., SFRAME_VERSION_2 is supported by the textual dump facilities. bfd/ * elf-sframe.c (_bfd_elf_merge_section_sframe): Generate an output SFrame section with version SFRAME_VERSION_2. Also, error out if the SFrame sections do not all have SFRAME_VERSION_2. * elfxx-x86.c (_bfd_x86_elf_create_sframe_plt): Generate SFrame section for plt entries with version SFRAME_VERSION_2. gas/ * gen-sframe.c (sframe_set_version): Update to SFRAME_VERSION_2. (output_sframe): Likewise. gas/testsuite/ * gas/cfi-sframe/cfi-sframe-aarch64-1.d: Use SFRAME_VERSION_2. * gas/cfi-sframe/cfi-sframe-aarch64-2.d: Likewise. * gas/cfi-sframe/cfi-sframe-aarch64-pac-ab-key-1.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-1.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-2.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-3.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-4.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-5.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-6.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-7.d: Likewise. * gas/cfi-sframe/cfi-sframe-common-8.d: Likewise. * gas/cfi-sframe/cfi-sframe-x86_64-1.d: Likewise. * gas/cfi-sframe/common-empty-1.d: Likewise. * gas/cfi-sframe/common-empty-2.d: Likewise. * gas/cfi-sframe/common-empty-3.d: Likewise. ld/testsuite/ * ld-aarch64/sframe-simple-1.d: Adjust for SFRAME_VERSION_2. * ld-x86-64/sframe-plt-1.d: Likewise. * ld-x86-64/sframe-simple-1.d: Likewise. libsframe/ * libsframe.ver: Add the new APIs. * sframe.c (sframe_decoder_get_funcdesc_v2): New definition. (sframe_encoder_add_funcdesc_v2): Likewise. (sframe_header_sanity_check_p): Include SFRAME_VERSION_2. (sframe_fre_check_range_p): Get rep_block_size info from SFrame FDE. * sframe-dump.c (dump_sframe_header): Add support for SFRAME_VERSION_2. (dump_sframe): Inform user if SFrame section in SFRAME_VERSION_1 format is seen. libsframe/testsuite/ * libsframe.decode/DATA-BE: Regenerated data file. * libsframe.decode/DATA1: Likewise. * libsframe.decode/DATA2: Likewise. * libsframe.find/plt-findfre-1.c: Use new API in the testcase. include/ * sframe.h: Add member to encode size of the code block of repeating instructions. Add 2 bytes of padding. * sframe-api.h (sframe_decoder_get_funcdesc_v2): New declaration. (sframe_encoder_add_funcdesc_v2): Likewise.
2023-06-28aarch64: Remove version dependencies from featuresAndrew Carlotti12-11/+12
Many instructions were enabled only when both a feature flag and a minimum architecture version are specified. This behaviour differs from GCC, which (in most cases) allows features to be enabled at any architecture version. There is no need for the toolchain to restrict combinations of unrelated features in this way, so this patch removes the unnecessary dependencies.
2023-06-28LoongArch: gas: Add LSX and LASX instructions testmengqinggang2-0/+2912
gas/ChangeLog: * testsuite/gas/loongarch/vector.d: New test. * testsuite/gas/loongarch/vector.s: New test.
2023-06-28LoongArch: gas: Add lsx and lasx instructions supportmengqinggang1-0/+4
gas/ChangeLog: * config/tc-loongarch.c (md_parse_option): Add lsx and lasx option. (loongarch_after_parse_args): Add lsx and lasx option. opcodes/ChangeLog: * loongarch-opc.c (struct loongarch_ase): Add lsx and lasx instructions.
2023-06-28LoongArch: Add R_LARCH_64_PCREL relocation supportmengqinggang3-3/+15
Gas defaults to emit R_LARCH_ADD64/R_LARCH_SUB64 unless explcitly declared to emit R_LARCH_64_PCREL. The LoongArch ABI at here: https://github.com/loongson/la-abi-specs/blob/release/la-abi.adoc bfd/ChangeLog: * bfd-in2.h (not): Add R_LARCH_64_PCREL * elfnn-loongarch.c (perform_relocation): Likewise. * elfxx-loongarch.c: Likewise. * libbfd.h: Likewise. * reloc.c: Likewise. gas/ChangeLog: * config/tc-loongarch.c (loongarch_args_parser_can_match_arg_helper): (md_apply_fix): Add R_LARCH_64_PCREL. * testsuite/gas/loongarch/64_pcrel.d: New test. * testsuite/gas/loongarch/64_pcrel.s: New test. include/ChangeLog: * elf/loongarch.h (RELOC_NUMBER): Add R_LARCH_64_PCREL. ld/ChangeLog: * testsuite/ld-loongarch-elf/ld-loongarch-elf.exp: Add test. * testsuite/ld-loongarch-elf/64_pcrel.d: New test. * testsuite/ld-loongarch-elf/64_pcrel.s: New test.
2023-06-27 RISC-V: Support Zicond extensionPhilipp Tomsich2-0/+15
This implements the Zicond (conditional integer operations) extension, as of version 1.0-rc2. The Zicond extension acts as a building block for branchless sequences including conditional-arithmetic, conditional-logic and conditional-select/move. The following instructions constitute Zicond: - czero.eqz rd, rs1, rs2 => rd = (rs2 == 0) ? 0 : rs1 - czero.nez rd, rs1, rs2 => rd = (rs2 != 0) ? 0 : rs1 See https://github.com/riscv/riscv-zicond/releases/download/v1.0-rc2/riscv-zicond-v1.0-rc2.pdf for the proposed specification and usage details. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Recognize INSN_CLASS_ZICOND. (riscv_multi_subset_supports_ext): Recognize INSN_CLASS_ZICOND. gas/ChangeLog: * testsuite/gas/riscv/zicond.d: New test. * testsuite/gas/riscv/zicond.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CZERO_EQZ): Define. (MASK_CZERO_EQZ): Define. (MATCH_CZERO_NEZ): Define, (MASK_CZERO_NEZ): Define. (DECLARE_INSN): Add czero.eqz and czero.nez. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZICOND. opcodes/ChangeLog: * riscv-opc.c: Add czero.eqz and czero.nez. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2023-06-26Fix gas tests for aarch64-peNick Clifton120-9/+363
2023-06-25LoongArch: Support referring to FCSRs as $fcsrXFeiyang Chen3-5/+32
Previously, FCSRs were referred to as $rX, which seemed strange. We refer to FCSRs as $fcsrX, which ensures compatibility with LLVM IAS as well. gas/ChangeLog: * config/tc-loongarch.c: (loongarch_fc_normal_name): New definition. (loongarch_fc_numeric_name): New definition. (loongarch_single_float_opcodes): Modify `movgr2fcsr` and `movfcsr2gr`. testsuite/gas/loongarch/float_op.d: Likewise. testsuite/gas/loongarch/float_op.s: Likewise. include/ChangeLog: * opcode/loongarch.h: (loongarch_fc_normal_name): New extern. (loongarch_fc_numeric_name): New extern. opcodes/ChangeLog: * opcodes/loongarch-dis.c (loongarch_after_parse_args): Support referring to FCSRs as $fcsrX. * opcodes/loongarch-opc.c (loongarch_args_parser_can_match_arg_helper): Likewise. Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
2023-06-22Revert "x86: Don't check if AVX512 template requires AVX512VL"H.J. Lu1-2/+3
This reverts commit c7face14225296a2f5d3ebeb8ace88c166d80c3e.
2023-06-20x86: Don't check if AVX512 template requires AVX512VLH.J. Lu1-3/+2
If the ZMM operand in an AVX12 template also allows XMM or ZMM, this template must require AVX512VL. Drop the AVX512VL requirement check on such AVX512 templates. * config/tc-i386.c (check_VecOperands): Don't check if AVX512 template requires AVX512VL.
2023-06-19riscv: Use run-time endianess for floating point literalsAndreas Schwab4-1/+20
gas/ PR binutils/30551 * config/tc-riscv.c (md_atof): Use target_big_endian instead of TARGET_BYTES_BIG_ENDIAN. * testsuite/gas/riscv/float-be.d: New file. * testsuite/gas/riscv/float-le.d: New file. * testsuite/gas/riscv/float.s: New file.
2023-06-16LoongArch: Fix ld "undefined reference" error with --enable-sharedmengqinggang1-1/+1
Because _bfd_read_unsigned_leb128 is hidden visibility, so it can't be referenced out of shared object. The new function loongarch_get_uleb128_length just used to call _bfd_read_unsigned_leb128. bfd/ChangeLog: * elfxx-loongarch.c (loongarch_get_uleb128_length): New function. * elfxx-loongarch.h (loongarch_get_uleb128_length): New function. gas/ChangeLog: * config/tc-loongarch.c (md_apply_fix): Use loongarch_get_uleb128_length.
2023-06-16x86: shrink Masking insn attribute to a single bit (boolean)Jan Beulich1-29/+18
The logic can actually be expressed with less code that way, utilizing that there are common patterns of when which form of masking is permitted. This then also eliminates the large set of open-codings of BOTH_MASKING in the opcode table.
2023-06-15MIPS/GAS/testsuite: Fix `-modd-spreg'/`-mno-odd-spreg' test invocationsMaciej W. Rozycki1-5/+8
Reformat `-modd-spreg'/`-mno-odd-spreg' test invocations in mips.exp to fit in 79 columns gas/ * testsuite/gas/mips/mips.exp: Reformat `-modd-spreg'/`-mno-odd-spreg' test invocations.
2023-06-15Add additional missing Allegrex CPU instructionsDavid Guillen Fandos3-0/+99
Allegrex supports some MIPS32 and MIPS32r2 instructions (albeit with some encoding differences) such as bit manipulation (ins/ext) and MLA (madd/msub). It also features some new instructions like wsbw and min/max or device-specific ones such as mfic. Signed-off-by: David Guillen Fandos <david@davidgf.net>
2023-06-15Add rotation instructions to MIPS Allegrex CPUDavid Guillen Fandos2-2/+2
The Allegrex CPU supports bit rotation instructions as described in the MIPS32 release 2 CPU (even though it is a MIPS-2 based CPU). Signed-off-by: David Guillen Fandos <david@davidgf.net>
2023-06-15Add MIPS Allegrex CPU as a MIPS2-based CPUDavid Guillen Fandos13-18/+633
The Allegrex CPU was created by Sony Interactive Entertainment to power their portable console, the PlayStation Portable. The pspdev organization maintains all sorts of tools to create software for said device including documentation. Signed-off-by: David Guillen Fandos <david@davidgf.net>
2023-06-15GAS/doc: Correct Tag_GNU_MIPS_ABI_MSA attribute descriptionMaciej W. Rozycki1-3/+4
Rewrite the paragraph to match the style of Tag_GNU_MIPS_ABI_FP text immediately above, correcting grammar and formatting at the same time. gas/ * doc/as.texi (MIPS Attributes): Correct Tag_GNU_MIPS_ABI_MSA attribute description.
2023-06-15Revert "MIPS: gas: alter 64 or 32 for mipsisa triples if march is implicit"Maciej W. Rozycki2-162/+122
This reverts commit 094025a30bb2da19df3990e0c0ff8167af823aa1. It was applied unapproved.
2023-06-15Revert "MIPS: default r6 if vendor is img"Maciej W. Rozycki2-14/+2
This reverts commit be0d391f22fe6009c3be907753975a984cbbcc23. It was applied unapproved.
2023-06-15Revert "MIPS: fix r6 testsuites"Maciej W. Rozycki155-354/+183
This reverts commit ffc528aed56b9e2c171137da28690a9bb6861b0b. It was applied unapproved.
2023-06-15Revert "MIPS: fix -gnuabi64 testsuite"Maciej W. Rozycki35-682/+461
This reverts commit cb81e84c72933a7fad10b75b7e270d92d8d65251. It was applied unapproved.
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