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2024-12-09LoongArch: Assign DWARF register numbers to register aliasesLulu Cai4-17/+780
.cfi directives only support the use of register numbers and not register names or aliases. This commit adds support for 4 formats, for example: .cfi_offset r1, 8 .cfi_offset ra, 8 .cfi_offset $r1,8 .cfi_offset $ra,8 The above .cfi directives are equivalent and all represent dwarf register number 1. Display register aliases as specified in the psABI during disassembly.
2024-12-05Support Intel AVX10.2 satcvt instructionsHu, Lin114-0/+2416
In this patch, we will support AVX10.2 satcvt instructions. All of them are new instruction forms. In current documentation, it is still VCVTTNEBF162I[,U]BS, but it will change to VCVTTBF162I[,U]BS eventually. In table part, we used temporary <sign> iterator to reduce redundancy. It definitely could be done for legacy cvt insns, but it is out of this patch's scope. gas/ChangeLog: * testsuite/gas/i386/i386.exp: Add AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-512-satcvt-intel.d: New test. * testsuite/gas/i386/avx10_2-512-satcvt.d: Ditto. * testsuite/gas/i386/avx10_2-512-satcvt.s: Ditto. * testsuite/gas/i386/avx10_2-256-satcvt-intel.d: Ditto. * testsuite/gas/i386/avx10_2-256-satcvt.d: Ditto. * testsuite/gas/i386/avx10_2-256-satcvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-satcvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-satcvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-satcvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-satcvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-satcvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-satcvt.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Add PREFIX_EVEX_MAP5_68, PREFIX_EVEX_MAP5_69, PREFIX_EVEX_MAP5_6A, PREFIX_EVEX_MAP5_6B, PREFIX_EVEX_MAP5_6C, PREFIX_EVEX_MAP5_6D. * i386-dis-evex-w.h: Add EVEX_W_MAP5_6C_P_0, EVEX_W_MAP5_6C_P_2, EVEX_W_MAP5_6D_P_0, EVEX_W_MAP5_6D_P_2. * i386-dis-evex.h (prefix_table): Add PREFIX_EVEX_MAP5_68, * PREFIX_EVEX_MAP5_69, PREFIX_EVEX_MAP5_6A, PREFIX_EVEX_MAP5_6B. * i386-dis.c: (PREFIX_EVEX_MAP5_68): New. (PREFIX_EVEX_MAP5_69): Ditto. (PREFIX_EVEX_MAP5_6A): Ditto. (PREFIX_EVEX_MAP5_6B): Ditto. (PREFIX_EVEX_MAP5_6C): Ditto. (PREFIX_EVEX_MAP5_6D): Ditto. (EVEX_MAP5_6C_P_0): Ditto. (EVEX_MAP5_6C_P_2): Ditto. (EVEX_MAP5_6D_P_0): Ditto. (EVEX_MAP5_6D_P_2): Ditto. * i386-opc.tbl: Add AVX10.2 instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto. Co-authored-by: Zewei Mo <zewei.mo@intel.com> Co-authored-by: Haochen Jiang <haochen.jiang@intel.com> Co-authored-by: Levy Hsu <admin@levyhsu.com>
2024-12-05x86: Eliminate unnecessary {evex} prefixesH.J. Lu6-0/+86
For several instructions including vps{l,r}l{d,q,w,dq} and vpsra{d,w}, their VEX part do not have the following version: vpsrlw $0x1f,(%r15,%rcx,4),%xmm0 Thus, {evex} prefix should not be inserted when their second operand is memory, while we still need them for register as second operand. Add a new macro %ME to solve this problem. For vpsraq, there is no VEX version, so the {evex} prefix should always be eliminated. gas/ChangeLog: PR binutils/32403 * testsuite/gas/i386/i386.exp: Run new test. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/evex-only.d: New test. * testsuite/gas/i386/evex-only.s: Ditto. * testsuite/gas/i386/x86-64-evex-only.d: Ditto. * testsuite/gas/i386/x86-64-evex-only.s: Ditto. opcodes/ChangeLog: PR binutils/32403 * i386-dis-evex-reg.h: Use %ME instead of %XE for vps{l,r}l{w,dq} and vpsraw. Split table for vpsra{d,q}. * i386-dis-evex-w.h: Use %ME instead of %XE for vps{l,r}l{d,q} and vpsrad. Eliminate vpsraq {evex} prefix. * i386-dis-evex.h: Split table for vpsra{d,q}. * i386-dis.c: (EVEX_W_0F72_R_4): New. (EVEX_W_0FE2): Ditto. (struct dis386): Add comment for %ME. (putop): Handle %ME. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com> Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2024-12-03gas: Re-enable .org test 1 on all targets except kvxJens Remus1-1/+1
It got erroneously disabled for all targets including kvx instead of excluding kvx only. gas/testsuite/ * gas/all/org-1.d: Re-enable on all targets except kvx. Fixes: 6e712424f5cb ("kvx: New port.") Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-12-03s390: Enable .bss/.struct data allocation directives testsJens Remus2-2/+2
This reduces the number of unsupported tests on s390 by two. gas/testsuite/ * gas/elf/bss.d: Enable for s390*-*-*. * gas/elf/bad-bss.d: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-12-03PowerPC: Add support for RFC02680 - PQC Acceleration InstructionsSurya Kumari Jangala2-0/+20
opcodes/ * ppc-opc.c (powerpc_opcodes): Add xvadduwm, xvadduhm, xvsubuwm, xvsubuhm, xvmuluwm, xvmuluhm, xvmulhsw, xvmulhsh, xvmulhuw, xvmulhuh. gas/ * testsuite/gas/ppc/future.s: New test. * testsuite/gas/ppc/future.d: Likewise.
2024-12-03gas: partly restore how current_location() had workedJan Beulich6-14/+27
Commit 4a826962e760 changed its behavior without saying why, and without putting in place any testcase demonstrating the required behavior. Firmly latch the current position unless deferred-evaluation mode is in effect.
2024-12-03MMIX: use current_location() directlyJan Beulich2-16/+3
It's no longer a static function, so it can be used without involving a wrapper function plus an indirect function call.
2024-12-03gas: streamline expr_build_dot()Jan Beulich1-11/+18
There's no point involving symbol_clone_if_forward_ref(), just for it to replace dot_symbol by one obtained from symbol_temp_new_now(). For the abs-section case also produce a slightly more "complete" (as in: all potentially relevant fields filled) expression by going through expr_build_uconstant(). Move the function next to current_location(), for it to be easier to see the (dis)similarities. Correct the function's comment while there.
2024-12-03Support Intel AVX10.2 BF16 instructionsKong Lingling14-0/+2323
In this patch, we will support AVX10.2 BF16 instructions. All of them are new instructions forms. In current documentation, it is still VSCALEFPBF16, but it will change to VSCALEFNEPBF16 eventually. In disassembler part, we added %XB to reduce W table pass since all of them get evex.w=0. gas/Changelog: * testsuite/gas/i386/i386.exp: Add AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-256-bf16-intel.d: New. * testsuite/gas/i386/avx10_2-256-bf16.d: Ditto. * testsuite/gas/i386/avx10_2-256-bf16.s: Ditto. * testsuite/gas/i386/avx10_2-512-bf16-intel.d: Ditto. * testsuite/gas/i386/avx10_2-512-bf16.d: Ditto. * testsuite/gas/i386/avx10_2-512-bf16.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-bf16-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-bf16.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-bf16.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-bf16-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-bf16.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-bf16.s: Ditto. opcodes/ * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F. Add PREFIX_EVEX_MAP6_2C, PREFIX_EVEX_MAP6_4C, PREFIX_EVEX_MAP6_4E, PREFIX_EVEX_MAP6_98, PREFIX_EVEX_MAP6_9A, PREFIX_EVEX_MAP6_9C, PREFIX_EVEX_MAP6_9E, PREFIX_EVEX_MAP6_A8, PREFIX_EVEX_MAP6_AA, PREFIX_EVEX_MAP6_AC, PREFIX_EVEX_MAP6_AE, PREFIX_EVEX_MAP6_B8, PREFIX_EVEX_MAP6_BA, PREFIX_EVEX_MAP6_BC, PREFIX_EVEX_MAP6_BE. * i386-dis-evex.h (evex_table): Update PREFIX_EVEX_MAP6_2C, PREFIX_EVEX_MAP6_42, PREFIX_EVEX_MAP6_4C, PREFIX_EVEX_MAP6_4E, PREFIX_EVEX_MAP6_98, PREFIX_EVEX_MAP6_9A, PREFIX_EVEX_MAP6_9C, PREFIX_EVEX_MAP6_9E, PREFIX_EVEX_MAP6_A8, PREFIX_EVEX_MAP6_AA, PREFIX_EVEX_MAP6_AC, PREFIX_EVEX_MAP6_AE, PREFIX_EVEX_MAP6_B8, PREFIX_EVEX_MAP6_BA, PREFIX_EVEX_MAP6_BC, PREFIX_EVEX_MAP6_BE. * i386-dis.c (PREFIX_EVEX_MAP6_2C): New enum. (PREFIX_EVEX_MAP6_42): Ditto. (PREFIX_EVEX_MAP6_4C): Ditto. (PREFIX_EVEX_MAP6_4E): Ditto. (PREFIX_EVEX_MAP6_98): Ditto. (PREFIX_EVEX_MAP6_9A): Ditto. (PREFIX_EVEX_MAP6_9C): Ditto. (PREFIX_EVEX_MAP6_9E): Ditto. (PREFIX_EVEX_MAP6_A8): Ditto. (PREFIX_EVEX_MAP6_AA): Ditto. (PREFIX_EVEX_MAP6_AC): Ditto. (PREFIX_EVEX_MAP6_AE): Ditto. (PREFIX_EVEX_MAP6_B8): Ditto. (PREFIX_EVEX_MAP6_BA): Ditto. (PREFIX_EVEX_MAP6_BC): Ditto. (PREFIX_EVEX_MAP6_BE): Ditto. (putop): Handle %XB. * i386-opc.tbl: Add AVX10.2 instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto. Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2024-12-02x86: default to not accepting MPX insnsJan Beulich28-30/+36
Gcc9 had MPX support removed. While we don't want to remove support, require these deprecated insns (and registers) to be enabled explicitly.
2024-12-02x86: always set ISA_1_BASELINE property for 64-bit objectsJan Beulich2-3/+4
The baseline was, afaik, specifically chosen to align with the baseline ISA of x86-64. It therefore makes no sense to emit that property only conditionally; if anything it confuses tools analyzing the difference between generated object files, which may result from just added / changed / removed (entirely ISA-independent) code, without any change to the enabled extensions. Compilers, after all, are free to use these baseline "extensions" when generating 64-bit code. While changing the one testcase that needs adjustment, also correct its misleading name (to be in sync with the filename).
2024-12-02x86/COFF: support section-index relocations in insn operandsJan Beulich6-2/+63
On the grounds of the principle put down near the bottom of [1], along with image and section relative operations, let's also support as insn operands what .secidx is for on the data side (of course like elsewhere the reloc operator can then also be used for data generation, albeit a small tweak to x86_cons() is needed for this to work). [1] https://sourceware.org/pipermail/binutils/2024-November/137617.html
2024-12-02x86/COFF: support RVA (image-relative) relocations in insn operandsJan Beulich7-2/+154
As was pointed out in [1] compilers produce code using such constructs, and hence we'd better support this. In analogy to the .rva directive permit @rva to be used for this, and in analogy with other architectures (plus to not diverge from e.g. Clang's integrated assembler, albeit I haven't been able myself to confirm it knows this form) also permit @imgrel. While there also adjust the operand type specifier for the adjacent @secrel32 - 64-bit fields cannot be used with a 32-bit relocation. Further while there also deal with *-*-pe* in x86-64.exp, even if (right now) perhaps only for completeness. [1] https://sourceware.org/pipermail/binutils/2024-November/137548.html
2024-12-02RISC-V: Add support for ssdbltrp and smdbltrp extension.Dongyan Chen4-2/+9
This implements the ssdbltrp extensons, version 1.0[1] and the smdbltrp extensions, version1.0[2]. [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc [2] https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc bfd/ChangeLog: * elfxx-riscv.c: Add 'ssdbltrp' and 'smdbltrp' to the list of konwn standard extensions. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/imply.d: Ditto. * testsuite/gas/riscv/imply.s: Ditto. * testsuite/gas/riscv/march-help.l: Ditto.
2024-11-29s390: Simplify parsing of omitted index register operandJens Remus1-16/+8
The index register operand X in D(X,B) can optionally be omitted by coding D(,B) or D(B). Simplify the parsing logic. gas/ * config/tc-s390.c (md_gather_operands): Rename omitted_base_or_index to omitted_index and simplify logic. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-11-29s390: Treat addressing operand sequence as one in disassemblerJens Remus1-1/+1
Reuse logic introduced with the preceding commit in the assembler to treat addressing operand sequences D(X,B), D(B), and D(L,B) as one with regards to optional last operands (i.e. optparm and optparm2). With this "nop" now disassembles into "nop" instead of "nop 0". opcodes/ * s390-dis.c (operand_count): New helper to count the remaining operands, treating D(X,B), D(B), and D(L,B) as one. (skip_optargs_p): New helper to test whether remaining operands are optional. (skip_optargs_zero_p): New helper to test whether remaining operands are optional and their values are zero. (s390_print_insn_with_opcode): Use skip_optargs_zero_p to skip optional last operands with a value of zero. gas/testsuite/ * gas/s390/zarch-optargs.d (nop): Adjust test case accordingly. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-11-29s390: Treat addressing operand sequence as one in assemblerJens Remus1-14/+34
The assembler erroneously treated any number of operands as optional, if the instruction was flagged to have one or two optional operands (i.e. optparm or optparm2). Only treat the exact specified number of operands as optional while treating addressing operand sequences D(X,B), D(B), and D(L,B) as one operand. gas/ * config/tc-s390.c (operand_count): New helper to count the remaining operands, treating D(X,B), D(B), and D(L,B) as one. (skip_optargs_p): Use new helper operand_count to treat D(X,B), D(B), and D(L,B) as one operand. (md_gather_operands): Use skip_optargs_p to skip only the optional last operands. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-11-29s390: Fix disassembly of optional addressing operandsJens Remus2-8/+84
"nop D1(B1)" erroneously disassembled into "nop D1(B1" (missing closing parenthesis). "nop D1(X1,0)" and "nop D1(X1,)" erroneously disassembled into "nop D1(X1)" (missing zero base register) instead of "nop D1(X1,0)". Do not skip disassembly of optional operands if they are index (X) or base (B) registers or length (L) in an addressing operand sequence "D(X,B)", "D(B)", or "D(L,B). Index and base register operand values of zero are being handled separately, as they may not be omitted unconditionally. For instance a base register value of zero must be printed in above mentioned case, to distinguish the index from the base register. This also ensures proper formatting of addressing operand sequences. While at it add further test cases for instructions with optional operands. opcodes/ * s390-dis.c (s390_print_insn_with_opcode): Do not unconditionally skip disassembly of optional operands with a value of zero, if within an addressing operand sequence. gas/testsuite/ * gas/s390/zarch-optargs.d: Add further test cases for instructions with optional operands. * gas/s390/zarch-optargs.s: Likewise. Reported-by: Florian Krohm <flo2030@eich-krohm.de> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-11-29x86: restrict gas'es recognition of -s to SolarisJan Beulich1-3/+8
When there for Solaris compatibility only, also recognize it only there. This way the option becomes available for other possible uses. While adjusting md_shortopts[], also re-arrange things such that we have only a single, uniform definition of it.
2024-11-29x86/Solaris: support Sun form of CMOVccJan Beulich4-0/+80
Sun specifies an alternative form for CMOVcc [1], which for some reason we never cared to support, even if - as per gcc's configure checking for it - it may have been the only permitted form at some point. While documentation doesn't indicate FCMOVcc to have similar alternative forms, gcc assumes so. Hence cover FCMOVcc as well. [1] https://docs.oracle.com/cd/E37838_01/html/E61064/ennbz.html#XALRMeoizm
2024-11-29x86: purge most *avx512*ig*-intel testsJan Beulich24-6996/+4
Having just one each (AVX512F) ought to be sufficient to cover Intel syntax disassembly. In x86-64.exp also reorder tests some, so that related ones are again next to each other, rather than being interspersed with APX ones.
2024-11-27Re: nios2: Remove binutils support for Nios II targetAlan Modra1-2/+0
Remove a now unused config file, regenerate POTFILES to remove nios2 refs, and modify config.bfd to report the target is obsolete.
2024-11-26nios2: Remove binutils support for Nios II target.Sandra Loosemore233-11682/+3
The Nios II architecture has been EOL'ed by the vendor. This patch removes all binutils, bfd, gas, binutils, and opcodes support for this target with the exception of the readelf utility. (The ELF EM_* number remains valid and the relocation definitions from the Nios II ABI will never change in future, so retaining the readelf support seems consistent with its purpose as a utility that tries to parse the headers in any ELF file provided as an argument regardless of target.)
2024-11-25Updated Bulgarian, Romanian and French translations for various ↵Nick Clifton1-4192/+3762
sub-directories. New Georgian translation for the gold sub-directory.
2024-11-22RISC-V: Support SiFive extensions: xsfvqmaccdod, xsfvqmaccqoq and ↵Nelson Chu7-2/+59
xsfvfnrclipxfqf Those SiFive extensions have been published on the web for a while, and we plan to implement intrinsics in GCC for those instructions soon. NOTE: The original patch was written by Nelson when he was still working at SiFive, and Kito rebased it to the trunk. Therefore, I kept the author as Nelson with his SiFive email. Document links: xsfvqmaccdod: https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification xsfvqmaccqoq: https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification xsfvfnrclipxfqf: https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
2024-11-20PowerPC: Add support for RFC02677 - VSX Vector Rotate Left WordPeter Bergner2-0/+2
opcodes/ * ppc-opc.c (powerpc_opcodes): Add xvrlw. gas/ * testsuite/gas/ppc/future.s: Add test for xvrlw. * testsuite/gas/ppc/future.d: Likewise.
2024-11-20arm: Support pac_key_* register operand for MRS/MSR in Armv8.1-M MainlineAndre Vieira3-1/+231
Add support for pac_key_[pu]_[0-3](_ns)? register operands for the MRS and MSR instructions when assembling for Armv8.1-M Mainline, as well as adding the corresponding support for disassembling instructions that use it.
2024-11-20RISC-V: Add Zcmt instructions and csr.Jiawei14-0/+93
This patch supports Zcmt[1] instruction 'cm.jt' and 'cm.jalt'. Add new CSR jvt for tablejump using. Since 'cm.jt' and 'cm.jalt' have the same instructiong encoding, use 'match_cm_jt' and 'match_cm_jalt' check the 'zcmt_index' field to distinguish them. [1] https://github.com/riscvarchive/riscv-code-size-reduction/releases Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): New CSR. (riscv_csr_address): Ditto. (validate_riscv_insn): New operand. (riscv_ip): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New CSR. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extension. * testsuite/gas/riscv/zcmt-fail.d: New test. * testsuite/gas/riscv/zcmt-fail.l: New test. * testsuite/gas/riscv/zcmt-fail.s: New test. * testsuite/gas/riscv/zcmt.d: New test. * testsuite/gas/riscv/zcmt.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CM_JT): New opcode. (MASK_CM_JT): New mask. (MATCH_CM_JALT): New opcode. (MASK_CM_JALT): New mask. (CSR_JVT): New CSR. (DECLARE_INSN): New declaration. (DECLARE_CSR): Ditto. * opcode/riscv.h (EXTRACT_ZCMT_INDEX): New marco. (ENCODE_ZCMT_INDEX): Ditto. (enum riscv_insn_class): New class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): New operand. * riscv-opc.c (match_cm_jt): New function. (match_cm_jalt): Ditto.
2024-11-19Support x86 Intel MSR_IMMHu, Lin112-11/+145
gas/ChangeLog: * NEWS: Support x86 Intel MSR_IMM. * config/tc-i386.c (cpu_arch): Add MSR_IMM. (cpu_flags_match): Add MSR_IMM to APX_F related processing. (i386_assemble): WRMSRNS's first operand is imm32, so add MN_wrmsrns like MN_uwrmsr. * doc/c-i386.texi: Document .msr_imm. * testsuite/gas/i386/i386.exp: Run MSR_IMM tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/msr_imm-inval.l: New test. * testsuite/gas/i386/msr_imm-inval.s: Ditto. * testsuite/gas/i386/x86-64-msr_imm-intel.d: Ditto. * testsuite/gas/i386/x86-64-msr_imm.d: Ditto. * testsuite/gas/i386/x86-64-msr_imm.s: Ditto. opcodes/ChangeLog: * i386-dis.c: Add REG_VEX_MAP7_F6_L_0_W_0, PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64, X86_64_VEX_MAP7_F6_L_0_W_0_R_0, VEX_LEN_MAP7_F6, VEX_W_MAP7_F6_L_0. (reg_table): New entry for MSR_IMM. (prefix_table): Ditto. (x86_64_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (map7_f6_opcode): New variable for MAP7. (get_valid_dis386): Support MAP7. * i386-gen.c (cpu_flags): Add MSR_IMM. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (i386_cpu_flags): Add cpumsr_imm. * i386-opc.tbl: Add MSR_IMM instructions. * i386-tbl.h: Regenerated.
2024-11-18x86: rename SPACE_{,E}VEX_MAP<N>Jan Beulich1-21/+21
Map7 already has dual purpose for USER-MSR (and is to gain more for MSR-IMM), while Map5 is about to gain VEX uses for AMX extensions. Drop the not really meaningful infixes and (in the opcode table) prefixes, retaining merely EVexMap4 for encoding EVex128 at the same time.
2024-11-18x86: VP2INTERSECT{D,Q} have mask register destination groupJan Beulich16-244/+293
Much like AVX512-{4FMAPS,4VNNIW} have a constraint on their register source, there's a constraint (need to be even) on the destination register here. Adjust "good" test cases accordingly, and add a new test case to check the warning.
2024-11-18x86: generalize "implicit quad group" handlingJan Beulich6-33/+67
We'll want to re-use it for VP2INTERSECT{D,Q}. While there add a testcase for the similarly affected AVX512-4VNNIW insns.
2024-11-18gas: move had_errors() invocation in finishing of subsegsJan Beulich1-6/+6
Invoking this repeatedly in an inner loop is not only inefficient, but may lead to inconsistencies in e.g. the listings that the original comment author cared about. (Accept potential inconsistencies across distinct sections though, to cover all invocations of the function.)
2024-11-18ELF: SHF_STRINGS isn't really tied to SHF_MERGEJan Beulich3-23/+28
It's not overly useful without it, but the spec doesn't name any dependency between the two. People may want to use it for purely informational purposes, for example. Adjust, in particular, entity size processing to be engaged if either flag is set, as mandated by the spec.
2024-11-18ELF: SHF_MERGE vs SHT_NOBITSJan Beulich1-0/+3
bfd/merge.c puts in quite some effort to track mergable sections. That's all wasted for sections which don't have contents, as for them _bfd_write_merged_section() will never be called. With the combination not having any useful effect, also warn about this in gas.
2024-11-18gas/ELF: also reject merge entity size being zeroJan Beulich1-1/+1
This won't have any useful effect, so is at best marginally less bogus than a negative value. The change actually points out a flawed (for Arm) testcase: @ is a comment character there.
2024-11-18s390: Add arch15 Concurrent-Functions Facility insnsJens Remus2-0/+8
opcodes/ * s390-opc.txt: Add arch15 Concurrent-Functions Facility instructions. * s390-opc.c (INSTR_SSF_RRDRD2, MASK_SSF_RRDRD2): New SSF instruction format variant. gas/testsuite/ * gas/s390/zarch-arch15.d: Tests for arch15 Concurrent-Functions Facility instructions. * gas/s390/zarch-arch15.s: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-11-13gas: add .cv_ucomp and .cv_scomp pseudo-directivesMark Harmstone8-1/+356
Add .cv_ucomp and .cv_scomp pseudo-directives for object files for Windows targets, which encode compressed CodeView integers according to the algorithm in CVCompressData in https://github.com/Microsoft/microsoft-pdb/blob/master/include/cvinfo.h. This is essentially Microsoft's answer to the LEB128, though used in far fewer places. CodeView uses these to encode the "binary annotations" in the S_INLINESITE symbol, which express the relationship between code offsets and line numbers in inlined functions. This has to be done in the assembler as GCC doesn't know how many bytes each instruction takes up. There's no equivalent for this for MSVC or LLVM, as in both cases the assembler and compiler are integrated. .cv_ucomp represents an unsigned big-endian integer between 0 and 0x1fffffff, taking up 1, 2, or 4 bytes: Value between 0 and 0x7f: 0aaaaaaa -> 0aaaaaaa (identity-mapped) Value between 0x80 and 0x3fff: 00aaaaaa bbbbbbbb -> 10aaaaaa bbbbbbbb Value between 0x4000 and 0x1fffffff: 000aaaaa bbbbbbbb ccccccccc dddddddd -> 110aaaaa bbbbbbbb ccccccccc dddddddd .cv_scomp represents a signed big-endian integer between -0xfffffff and 0xfffffff, encoded according to EncodeSignedInt32 in cvinfo.h. The absolute value of the integer is shifted left one bit, the LSB set for a negative value, and the result expressed as if it were a .cv_ucomp: cv_scomp(x) = cv_ucomp((abs(x) << 1) | (x < 0 ? 1 : 0))
2024-11-08aarch64: testsuite: remove hard-coded instruction addressesMatthieu Longo1-26/+26
2024-11-08aarch64: remove redundant register type R_NMatthieu Longo1-5/+1
The register type R_N is redundant with R_ZR_SP. This patch removes it, and replaces its usage by R_ZR_SP.
2024-11-08aarch64: constify unchanged char* argumentsMatthieu Longo1-1/+1
2024-11-08arm, objdump: print obsolote warning when 26-bit set in instructionsAndre Vieira5-76/+36
Arm has obsoleted the 26-bit addressing mode. Diagnose this when disasembling these instructions by printing OBSOLETE.
2024-11-08arm, objdump: Make objdump use bfd's machine detection to drive disassemblyAndre Vieira4-17/+19
For any arm elf target, disable an old piece of code that forced disassembly to disassemble for 'unknown architecture' which once upon a time meant it would disassemble ANY arm instruction. This is no longer true with the addition of Armv8.1-M Mainline, as there are conflicting encodings for different thumb instructions. BFD however can detect what architecture the object file was assembled for using information in the notes section. So if available, we use that, otherwise we default to the old 'unknown' behaviour. With the changes above code, a mode changing 'bx lr' assembled for armv4 with the option --fix-v4bx will result in an object file that is recognized by bfd as one for the armv4 architecture. The disassembler now disassembles this encoding as a BX even for Armv4 architectures, but warns the user when disassembling for Armv4 that this instruction is only valid from Armv4T onwards. Remove the unused and wrongfully defined ARM_ARCH_V8A_CRC, and define and use a ARM_ARCH_V8R_CRC to make sure instructions enabled by -march=armv8-r+crc are disassembled correctly. Patch up some of the tests cases, see a brief explanation for each below. inst.d: This test checks the assembly & disassembly of basic instructions in armv3m. I changed the expected behaviour for teqp, cmnp cmpp and testp instructions to properly print p when disassembling, whereas before, in the 'unknown' case it would disassemble these as UNPREDICTABLE as they were changed in later architectures. nops.d: Was missing an -march, added one to make sure we were testing the right behavior of NOP<c> instructions. unpredictable.d: Was missing an -march, added armv6 as that reproduced the behaviour being tested.
2024-11-07arm: Skip two failing tests for wince & pe targetsAndre Simoes Dias Vieira2-0/+2
We don't seem to support any m-profile assembly/disassembly tests for wince or pe, so skipping the pacbti one too. The pr29494 test needs to be skipped because it uses assembly syntax that is not supported in wince/pe like for instance eabi_attribute directives.
2024-11-06PowerPC: Merge rfc2655 and rfc2656 test cases into one future test casePeter Bergner5-32/+18
gas/ * testsuite/gas/ppc/rfc02655.[ds]: Rename from this... * testsuite/gas/ppc/future.[ds]: ... to this. * testsuite/gas/ppc/rfc02656.[ds]: Delete. Move tests to future.[ds]. * testsuite/gas/ppc/ppc.exp: Update for file name changes.
2024-10-31gas/doc/riscv: Fixed misaligned instruction tableNelson Chu1-42/+42
gas/ * doc/c-riscv.texi: Fixed misaligned instruction table.
2024-10-30x86: add a helper to copy insn operand infoJan Beulich1-133/+44
We're doing such in fairly many places, and yet more are likely to appear; centralize the logic, much like we already have swap_2_operands(). While there also correct mis-indentation in adjacent code in process_operands().
2024-10-30x86/APX: support JMPABS also in assemblerJan Beulich5-8/+51
Without this APX support isn't really complete. For Intel syntax displacement form is needed, such that symbolic operands won't need prefixing by "offset". (The other form is actually not used at all in Intel syntax.) For the record: To restrict displacement form to Intel syntax is not something I actually agree with.
2024-10-30x86/APX: squash REX prefix when REX2 is being emittedJan Beulich3-1/+13
We should not (silently) emit a REX prefix ahead of a REX2-encoded insn; such encodings are illegal. Best we can do is fold the REX bits into the REX2 prefix, and then zap the REX one from i.prefix[].
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