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2022-09-30RISC-V: Relax "fmv.[sdq]" requirementsTsukasa OI6-0/+6
This commit relaxes requirements to "fmv.s" instructions from 'F' to ('F' or 'Zfinx'). The same applies to "fmv.d" and "fmv.q". Note that 'Zhinx' extension already contains "fmv.h" instruction (as well as 'Zfh'). gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Add "fmv.s" instruction. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Add "fmv.d" instruction. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.d: Add "fmv.q" instruction. * testsuite/gas/riscv/zqinx.s: Likewise. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Relax requirements to "fmv.[sdq]" instructions to support those in 'Zfinx'/'Zdinx'/'Zqinx'.
2022-09-30RISC-V: Reorganize and enhance 'Zfinx' testsTsukasa OI6-106/+207
This commit adds certain test cases for 'Zfinx'/'Zdinx'/'Zqinx' extensions and reorganizes them, fixing coding style while improving coverage. This is partially based on jiawei's 'Zhinx' testcases. gas/ChangeLog: * testsuite/gas/riscv/zfinx.s: Use different registers for better encode space testing. Make indentation consistent. Add tests for instruction with rounding mode. Change march to minimum required extensions. Remove source line. * testsuite/gas/riscv/zfinx.d: Likewise. * testsuite/gas/riscv/zdinx.s: Likewise. * testsuite/gas/riscv/zdinx.d: Likewise. * testsuite/gas/riscv/zqinx.s: Likewise. Also use even-numbered registers to use valid register pairs. * testsuite/gas/riscv/zqinx.d: Likewise. Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> Signed-off-by: jiawei <jiawei@iscas.ac.cn>
2022-09-30RISC-V: Eliminate long-casts of X_add_number in diagnosticsChristoph Müllner1-8/+8
There is no need for casts to (signed/unsigned) long, as we can use C99's PRId64/PRIu64 format specifiers.
2022-09-30RISC-V: fallout from "re-arrange opcode table for consistent alias handling"Jan Beulich4-14/+14
Several new testcasee have appeared since the submission of said change, some of which now also need adjustment.
2022-09-30RISC-V: fix build after "Add support for arbitrary immediate encoding formats"Jan Beulich1-4/+4
Pre- and post-increment/decrement are side effects, the behavior of which is undefined when combined with passing an address of the accessed variable in the same function invocation. There's no need for the increments here - simply adding 1 achieves the intended effect without triggering compiler diagnostics (which are fatal with -Werror).
2022-09-30RISC-V: drop stray INSN_ALIAS flagsJan Beulich2-0/+35
FENCE.TSO isn't an alias. ZIP and UNZIP in the long run likely are, but presently they aren't. This fixes disassembly of these insns with -Mno-aliases.
2022-09-30RISC-V: re-arrange opcode table for consistent alias handlingJan Beulich21-159/+375
For disassembly to pick up aliases in favor of underlying insns (helping readability in the common case), the aliases need to come ahead of the "base" insns. Slightly more code movement is needed because of insns with the same name needing to stay next to each other. Note that the "rorw" alias entry also has the missing INSN_ALIAS added here. Clone a few testcases to exercise -Mno-aliases some more, better covering the differences between the default and that disassembly mode.
2022-09-30x86: improve match_template()'s diagnosticsJan Beulich7-67/+86
At the example of extractps $0, %xmm0, %xmm0 insertps $0, %xmm0, %eax (both having respectively the same mistake of using the wrong kind of destination register) it is easy to see that current behavior is far from ideal: The former results in "unsupported instruction" for 32-bit code simply because the 2nd template we have is a Cpu64 one. Instead we should aim at emitting the "best" possible error, which will typically be the one where we passed the largest number of checks. Generalize the original "specific_error" approach by making it apply to the entire matching loop, utilizing that line numbers increase as we pass further checks.
2022-09-30x86/Intel: restrict suffix derivationJan Beulich6-61/+230
While in some cases deriving an AT&T-style suffix from an Intel syntax memory operand size specifier is necessary, in many cases this is not only pointless, but has led to the introduction of various workarounds: Excessive use of IgnoreSize and NoRex64 as well as the ToDword and ToQword attributes. Suppress suffix derivation when we can clearly tell that the memory operand's size isn't going to be needed to infer the possible need for the low byte/word opcode bit or an operand size prefix (0x66 or REX.W). As a result ToDword and ToQword can be dropped entirely, plus a fair number of IgnoreSize and NoRex64 can also be got rid of. Note that IgnoreSize needs to remain on legacy encoded SIMD insns with GPR operand, to avoid emitting an operand size prefix in 16-bit mode. (Since 16-bit code using SIMD insns isn't well tested, clone an existing testcase just enough to cover a few insns which are potentially problematic but are being touched here.) Note that while folding the VCVT{,T}S{S,D}2SI templates, VCVT{,T}SH2SI isn't included there. This is to fulfill the request of not allowing L and Q suffixes there, despite the inconsistency with VCVT{,T}S{S,D}2SI.
2022-09-30LoongArch: Update ELF e_flags handling according to specification.liuzhensong1-10/+10
Update handling of e_flags according to the documentation update [1] (discussions [2][3]). Object file bitness is now represented in the EI_CLASS byte. The e_flags field is now interpreted as follows: e_flags[2:0]: Base ABI modifier - 0x1: soft-float - 0x2: single-precision hard-float - 0x3: double-precision hard-float e_flags[7:6]: ELF object ABI version - 0x0: v0 - 0x1: v1 [1]: https://github.com/loongson/LoongArch-Documentation/blob/main/docs/LoongArch-ELF-ABI-EN.adoc#e_flags-identifies-abi-type-and-version [2]: https://github.com/loongson/LoongArch-Documentation/pull/61 [3]: https://github.com/loongson/LoongArch-Documentation/pull/47
2022-09-28The help document of as misses some many optionsNick Clifton4-34/+90
PR 29623 * as.c (show_usage): Document the --dump-config, --gdwarf-cie-version, --hash-size, --multibyte-handling, and --reduce-memory-overheads options. * config/tc-i386.c (md_show_usage): Document the -O option. * doc/as.texi: Document the --dump-config, --emulation, --hash-size, and --reduce-memory-overheads options.
2022-09-26binutils, gdb: support zstd compressed debug sectionsFangrui Song12-47/+380
PR29397 PR29563: Add new configure option --with-zstd which defaults to auto. If pkgconfig/libzstd.pc is found, define HAVE_ZSTD and support zstd compressed debug sections for most tools. * bfd: for addr2line, objdump --dwarf, gdb, etc * gas: support --compress-debug-sections=zstd * ld: support ELFCOMPRESS_ZSTD input and --compress-debug-sections=zstd * objcopy: support ELFCOMPRESS_ZSTD input for --decompress-debug-sections and --compress-debug-sections=zstd * gdb: support ELFCOMPRESS_ZSTD input. The bfd change references zstd symbols, so gdb has to link against -lzstd in this patch. If zstd is not supported, ELFCOMPRESS_ZSTD input triggers an error. We can avoid HAVE_ZSTD if binutils-gdb imports zstd/ like zlib/, but this is too heavyweight, so don't do it for now. ``` % ld/ld-new a.o ld/ld-new: a.o: section .debug_abbrev is compressed with zstd, but BFD is not built with zstd support ... % ld/ld-new a.o --compress-debug-sections=zstd ld/ld-new: --compress-debug-sections=zstd: ld is not built with zstd support % binutils/objcopy --compress-debug-sections=zstd a.o b.o binutils/objcopy: --compress-debug-sections=zstd: binutils is not built with zstd support % binutils/objcopy b.o --decompress-debug-sections binutils/objcopy: zstd.o: section .debug_abbrev is compressed with zstd, but BFD is not built with zstd support ... ```
2022-09-23RISC-V: Add Zawrs ISA extension supportChristoph Müllner3-0/+25
This patch adds support for the Zawrs ISA extension ("wrs.nto" and "wrs.sto" instructions). The specification can be found here: https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner6-0/+88
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadMemPair extension, a collection of T-Head specific two-GP-register memory operations. The 'th' prefix and the "XTheadMemPair" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add support for literal instruction argumentsChristoph Müllner1-0/+10
This patch introduces support for arbitrary literal instruction arguments, that are not encoded in the opcode. A typical use case for this feature would be an instruction that applies an implicit shift by a constant value on an immediate (that is a real operand). With this patch it is possible to make this shift visible in the dissasembly and support such artificial parameter as part of the asssembly code. Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head MemIdx vendor extensionChristoph Müllner6-0/+137
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadMemIdx extension, a collection of T-Head specific GPR memory access instructions. The 'th' prefix and the "XTheadMemIdx" extension are documented in a PR for the RISC-V toolchain conventions ([1]). In total XTheadCmo introduces the following 44 instructions (BU,HU,WU only for loads (zero-extend instead of sign-extend)): * {L,S}{D,W,WU,H,HU,B,BU}{IA,IB} rd, rs1, imm5, imm2 * {L,S}R{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2 * {L,S}UR{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2 [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head FMemIdx vendor extensionChristoph Müllner6-0/+85
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadFMemIdx extension, a collection of T-Head-specific floating-point memory access instructions. The 'th' prefix and the "XTheadFMemIdx" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head MAC vendor extensionChristoph Müllner3-0/+27
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadMac extension, a collection of T-Head-specific multiply-accumulate instructions. The 'th' prefix and the "XTheadMac" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head CondMov vendor extensionChristoph Müllner3-0/+19
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadCondMov extension, a collection of T-Head-specific conditional move instructions. The 'th' prefix and the "XTheadCondMov" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head Bitmanip vendor extensionChristoph Müllner16-0/+141
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XThead{Ba,Bb,Bs} extensions, a collection of T-Head-specific bitmanipulation instructions. The 'th' prefix and the "XThead{Ba,Bb,Bs}" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner1-0/+74
This patch introduces support for arbitrary signed or unsigned immediate encoding formats. The formats have the form "XsN@S" and "XuN@S" with N being the number of bits and S the LSB position. For example an immediate field of 5 bytes that encodes a signed value and is stored in the bits 24-20 of the instruction word can use the format specifier "Xs5@20". Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head SYNC vendor extensionChristoph Müllner6-0/+40
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadSync extension, a collection of T-Head-specific multi-processor synchronization instructions. The 'th' prefix and the "XTheadSync" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add T-Head CMO vendor extensionChristoph Müllner6-0/+103
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the XTheadCmo extension, a collection of T-Head specific cache management operations. The 'th' prefix and the "XTheadCmo" extension are documented in a PR for the RISC-V toolchain conventions ([1]). In total XTheadCmo introduces the following 21 instructions: * DCACHE.{C,CI,I}ALL * DCACHE.{C,CI,I}{PA,VA,SW} rs1 * DCACHE.C{PAL1,VAL1} rs1 * ICACHE.I{ALL,ALLS} * ICACHE.I{PA,VA} rs1 * L2CACHE.{C,CI,I}ALL Contrary to Zicbom, the XTheadCmo instructions don't have a constant displacement, therefore we have a different syntax for the arguments. To clarify this is intended behaviour, there is a set of negative test for Zicbom-style arguments in x-thead-cmo-fail.s. [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 v2: - Add missing DECLARE_INSN() list - Fix ordering Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add generic support for vendor extensionsChristoph Müllner1-0/+14
This patch introduces changes that allow the integration of vendor ISA extensions: * Define a list of vendor extensions (riscv_supported_vendor_x_ext) where vendor extensions can be added * Introduce a section with a table in the documentation where vendor extensions can be added To add a vendor extension that consists of instructions only, the following things need to be done: * Add the extension to the riscv_supported_vendor_x_ext list * Add lookup entry in riscv_multi_subset_supports * Documenting the extension in c-riscv.texti * Add test cases for all instructions * Add MATCH*/MASK* constants and DECLARE_INSN() for all instructions * Add new instruction class to enum riscv_insn_class * Define the instructions in riscv_opcodes * Additional changes if necessary (depending on the instructions) Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2022-09-22RISC-V: Add macro-only operands to validate_riscv_insnTsukasa OI1-0/+3
Although they are not (and should not be) reachable, following macro-only operands are parsed in the `validate_riscv_insn' function and ignored. That function also notes that they are macro-only. - "A" - "B" - "I" Following this convention, this commit adds three remaining macro-only operands to this function. By doing this, we could instead choose to reject those operands from appearing in regular instructions later. - "c" (used by call, tail and jump macros) - "VM" (used by vmsge.vx and vmsgeu.vx macros) - "VT" (likewise) gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add "c", "VM" and "VT" macro-only operand types.
2022-09-21RISC-V: Fix riscv_set_tso declarationTsukasa OI1-1/+1
To avoid -Werror=strict-prototypes, this commit changes () to (void). This is because "()" possibly means a function prototype with indeterminate arguments on old C standards. gas/ChangeLog: * config/tc-riscv.c (riscv_set_tso): Fix declaration.
2022-09-21RISC-V: Set EF_RISCV_TSO also on .option archTsukasa OI1-0/+3
This is a minor fix to commit 96462b012988d35ebb1137a2ad9fd0a96547d79a ("RISC-V: Implement Ztso extension"). Currently, it sets EF_RISCV_TSO ELF flag when initial ISA string contains the 'Ztso' extension. However, GAS has a way to update the ISA string: ".option arch". When the architecture is updated by ".option arch", EF_RISCV_RVC ELF flag is set when the 'C' extension is detected. Analogously, this commit sets the EF_RISCV_TSO when the 'Ztso' extension is detected. gas/ChangeLog: * config/tc-riscv.c (s_riscv_option): Set TSO ELF flag if the 'Ztso' extension is specified via ".option arch" directive.
2022-09-21RISC-V: Implement Ztso extensionShihua2-0/+19
This patch support ZTSO extension. It will turn on the tso flag for elf_flags once we have enabled Ztso extension. This is intended to implement v0.1 of the proposed specification which can be found in Chapter 25 of, https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf. bfd\ChangeLog: * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Set TSO flag. * elfxx-riscv.c: Add Ztso's arch. binutils\ChangeLog: * readelf.c (get_machine_flags): Set TSO flag. gas\ChangeLog: * config/tc-riscv.c (riscv_set_tso): Ditto. (riscv_set_arch): Ditto. * testsuite/gas/riscv/ztso.d: New test. include\ChangeLog: * elf/riscv.h (EF_RISCV_TSO): Ditto.
2022-09-21RISC-V: Always generate R_RISCV_CALL_PLT reloc for call in assembler.Nelson Chu3-8/+4
Since we have the same behaviors of CALL and CALL_PLT relocs in linker for now, https://github.com/bminor/binutils-gdb/commit/3b1450b38c644f99aa2e211747b428b9f8d15cca And the psabi already deprecate the CALL reloc, https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/a0dced85018d7a0ec17023c9389cbd70b1dbc1b0 Therefore, we should always generate R_RISCV_CALL_PLT reloc for call, even if it has @plt postfix. I believe LLVM (https://reviews.llvm.org/D132530) already support this, so GNU as should do the same thing. gas/ * config/tc-riscv.c (riscv_ip): Always generate CALL_PLT reloc for call, even if it has @plt postfix. * testsuite/gas/riscv/no-relax-reloc.d: Updated CALL to CALL_PLT. * testsuite/gas/riscv/relax-reloc.d: Likewise. ld/ * testsuite/ld-riscv-elf/variant_cc-r.d: Updated CALL to CALL_PLT.
2022-09-21Re: PowerPC64 pcrel got relocs against local symbolsAlan Modra1-6/+52
The last patch wasn't all that shiny. There are rather a lot more relocations that can hit the assertion in md_apply_fix if the symbol is local or absolute. Fix them all. * config/tc-ppc.c (ppc_force_relocation): Add all relocs that expect a symbol in md_apply_fix. Remove tls pcrel relocs already covered in general tls match range.
2022-09-21ppc/svp64: test setvl ms operandDmitry Selyutin2-0/+2
2022-09-20LoongArch: Set macro SUB_SEGMENT_ALIGN to 0.liuzhensong1-0/+2
2022-09-16PowerPC64 pcrel got relocs against local symbolsAlan Modra1-0/+6
Not that anyone would want to indirect via the GOT when an address can be loaded directly with pla, the following: pld 3,x@got@pcrel x: leads to "Internal error in md_apply_fix", because the generic parts of assembler fixup handling convert the fx_pcrel fixup to one without a symbol. Stop that happening. * config/tc-ppc.c (ppc_force_relocation): Add PLT_PCREL34 and assorted GOT_PCREL34 relocs.
2022-09-16RISC-V: Make g imply zmmul extension.Nelson Chu8-8/+8
bfd/ * elfxx-riscv.c (riscv_implicit_subset): Moved entry of m after g, so that g can imply zmmul. gas/ * testsuite/gas/riscv/attribute-01.d: Updated. * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-10.d: Likewise. * testsuite/gas/riscv/march-imply-g.d: Likewise. * testsuite/gas/riscv/march-imply-unsupported.d: Likewise.
2022-09-15bfd, binutils, gas: Remove/mark unused variablesTsukasa OI1-3/+0
Clang generates a warning on unused (technically, written but not read thereafter) variables. By the default configuration (with "-Werror"), it causes a build failure (unless "--disable-werror" is specified). This commit adds ATTRIBUTE_UNUSED attribute to some of them, which means they are *possibly* unused (can be used but no warnings occur when unused) and removes others. bfd/ChangeLog: * elf32-lm32.c (lm32_elf_size_dynamic_sections): Mark unused rgot_count variable. * elf32-nds32.c (elf32_nds32_unify_relax_group): Remove unused count variable. * mmo.c (mmo_scan): Mark unused lineno variable. binutils/ChangeLog: * windmc.c (write_rc): Remove unused i variable. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Remove unused argnum variable. ld/ChangeLog: * pe-dll.c (generate_reloc): Remove unused bi and page_count variables.
2022-09-14bfd: Stop using -Wstack-usage=262144 when built with ClangTsukasa OI1-0/+18
Some components of GNU Binutils will pass "-Wstack-usage=262144" when "GCC >= 5.0" is detected. However, Clang does not support "-Wstack-usage", despite that related configuration part in bfd/warning.m4 handles the latest Clang (15.0.0 as of this writing) as "GCC >= 5.0". The option "-Wstack-usage" was ignored when the first version of Clang is released but even this "ignoring" behavior is removed before Clang 4.0.0. So, if we give Clang "-Wstack-usage=262144", it generates a warning, making the build failure. This commit checks "__clang__" macro to prevent adding the option if the compiler is identified as Clang. bfd/ChangeLog: * warning.m4: Stop appending "-Wstack-usage=262144" option when compiled with Clang. * configure: Regenerate. binutils/ChangeLog: * configure: Regenerate. gas/ChangeLog: * configure: Regenerate. gold/ChangeLog: * configure: Regenerate. gprof/ChangeLog: * configure: Regenerate. ld/ChangeLog: * configure: Regenerate. opcodes/ChangeLog: * configure: Regenerate.
2022-09-12ppc: Document the -mfuture and -Mfuture options and make them usablePeter Bergner2-0/+5
The -mfuture and -Mfuture options which are used for adding potential new ISA instructions were not documented. They also lacked a bitmask so new instructions could not be enabled by those options. Fixed. binutils/ * doc/binutils.texi: Document -Mfuture. gas/ * config/tc-ppc.c: Document -mfuture * doc/c-ppc.texi: Likewise. include/ * opcode/ppc.h (PPC_OPCODE_FUTURE): Define. opcodes/ * ppc-dis.c (ppc_opts) <future>: Use it. * ppc-opc.c (FUTURE): Define.
2022-09-10Re: PR29466, APP/NO_APP with linefileAlan Modra1-1/+1
It looks like I copied the SIZE init across from binutils/testsuite/config/default.exp without some necessary editing. * testsuite/config/default.exp (SIZE): Adjust relative path.
2022-09-09RISC-V: Fix vector CSR requirementsTsukasa OI5-57/+57
Vector CSRs are also required on smaller vector subsets. Not only that the most of vector CSRs are general purpose (and must be accessible for every vector subsets), current minimum vector subset 'Zve32x' requires fixed point arithmetic, making remaining non-general purpose (fixed point arithmetic only) CSRs mandatory for such subsets. So, those CSRs must be accessible from 'Zve32x', not just from 'V'. This commit fixes this issue which caused CSR accessibility warnings. gas/ChangeLog: * config/tc-riscv.c (riscv_csr_address): Change vector CSR requirement from 'V' to 'Zve32x'. * testsuite/gas/riscv/csr-version-1p9p1.l: Change vector CSR requirement from 'V' to 'Zve32x'. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise.
2022-09-08Gas generated incorrect debug info (top-level DW_TAG_unspecified_type DIE)Nick Clifton6-30/+50
PR 29559 * dwarf2dbg.c (out_debug_info): Place DW_TAG_unspecified_type at the end of the list of children, not at the start of the CU information. * testsuite/gas/elf/dwarf-3-func.d: Update expected output. * testsuite/gas/elf/dwarf-5-func-global.d: Likewise. * testsuite/gas/elf/dwarf-5-func-local.d: Likewise. * testsuite/gas/elf/dwarf-5-func.d: Likewise.
2022-09-07LoongArch: fix gas BFD_RELOC_8/16/24 bugmengqinggang3-18/+58
If fixP->fx_subsy is NULL, BFD_RELOC_8/16/24 can't convert to BFD_RELOC_LARCH_xxx. gas/config/tc-loongarch.c
2022-09-02RISC-V: Print highest address (-1) on the disassemblerTsukasa OI6-0/+71
This patch makes possible to print the highest address (-1) and the addresses related to gp which value is -1. This is particularly useful if the highest address space is used for I/O registers and corresponding symbols are defined. Besides, despite that it is very rare to have GP the highest address, it would be nice because we enabled highest address printing on regular cases. gas/ChangeLog: * testsuite/gas/riscv/dis-addr-topaddr.s: New test for the top address (-1) printing. * testsuite/gas/riscv/dis-addr-topaddr-32.d: Likewise. * testsuite/gas/riscv/dis-addr-topaddr-64.d: Likewise. * testsuite/gas/riscv/dis-addr-topaddr-gp.s: New test for GP-relative addressing when GP is the highest address (-1). * testsuite/gas/riscv/dis-addr-topaddr-gp-32.d: Likewise. * testsuite/gas/riscv/dis-addr-topaddr-gp-64.d: Likewise. opcodes/ChangeLog: * riscv-dis.c (struct riscv_private_data): Add `to_print_addr' to enable printing the highest address. (maybe_print_address): Utilize `to_print_addr'. (riscv_disassemble_insn): Likewise.
2022-09-02RISC-V: PR29342, Fix RV32 disassembler address computationTsukasa OI4-1/+135
If either the base register is `zero', `tp' or `gp' and XLEN is 32, an incorrectly sign-extended address is produced when printing. This commit fixes this by fitting an address into a 32-bit value on RV32. Besides, H. Peter Anvin discovered that we have wrong address computation for JALR instruction (the initial bug is back in 2018). This commit also fixes that based on the idea of Palmer Dabbelt. gas/ pr29342 * testsuite/gas/riscv/lla32.d: Reflect RV32 address computation fix. * testsuite/gas/riscv/dis-addr-overflow.s: New testcase. * testsuite/gas/riscv/dis-addr-overflow-32.d: Likewise. * testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise. opcodes/ pr29342 * riscv-dis.c (maybe_print_address): Fit address into 32-bit on RV32. (print_insn_args): Fix JALR address by adding EXTRACT_ITYPE_IMM.
2022-09-02RISC-V: Add address printer tests with ADDIWTsukasa OI3-0/+64
Address sequences involving ADDIW/C.ADDIW instructions require special handling to sign-extend lower 32-bits of the original result. This commit tests whether this sign-extension works. gas/ChangeLog: * testsuite/gas/riscv/dis-addr-addiw.s: New to test the address computation with sign extension as used in ADDIW/C.ADDIW. * testsuite/gas/riscv/dis-addr-addiw-a.d: Test PC sign bit 0. * testsuite/gas/riscv/dis-addr-addiw-b.d: Test PC sign bit 1. gas/ChangeLog: * testsuite/gas/riscv/dis-addr-addiw-a.d: New test. * testsuite/gas/riscv/dis-addr-addiw-b.d: New test. * testsuite/gas/riscv/dis-addr-addiw.s: New test.
2022-08-31Add OpenBSD AArch64 GAS support.Frederic Cambus2-0/+5
* configure.tgt (aarch64*-*-openbsd*): Add target.
2022-08-30Add a testcase for PR 29494.Nick Clifton3-0/+10001
PR 29494 * testsuite/gas/arm/pr29494.s: New test source file. * testsuite/gas/arm/pr29494.d: New test driver.
2022-08-30LoongArch: Fix redefinition of "PACKAGE".liuzhensong1-1/+1
Running configure and make in binutils-gdb. $ ./configure $ make In file included from ./as.h:37, from ./config/loongarch-lex.l:21, from config/loongarch-lex-wrapper.c:20: ./config.h:206: error: “PACKAGE” redefined [-Werror] #define PACKAGE "gas" ... gas/config * loongarch-lex-wrapper.c
2022-08-30RISC-V: Add 'Zmmul' extension in assembler.Tsukasa OI15-2/+143
Three-part patch set from Tsukasa OI to support zmmul in assembler. The 'Zmmul' is a RISC-V extension consisting of only multiply instructions (a subset of 'M' which has multiply and divide instructions). bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Add 'Zmmul' implied by 'M'. (riscv_supported_std_z_ext): Add 'Zmmul' extension. (riscv_multi_subset_supports): Add handling for new instruction class. gas/ * testsuite/gas/riscv/attribute-09.d: Updated implicit 'Zmmul' by 'M'. * testsuite/gas/riscv/option-arch-02.d: Likewise. * testsuite/gas/riscv/m-ext.s: New test. * testsuite/gas/riscv/m-ext-32.d: New test (RV32). * testsuite/gas/riscv/m-ext-64.d: New test (RV64). * testsuite/gas/riscv/zmmul-32.d: New expected output. * testsuite/gas/riscv/zmmul-64.d: Likewise. * testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure by using RV64-only instructions in RV32). * testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise. * testsuite/gas/riscv/m-ext-fail-zmmul-32.d: New failure test (RV32 + Zmmul but with no M). * testsuite/gas/riscv/m-ext-fail-zmmul-32.l: Likewise. * testsuite/gas/riscv/m-ext-fail-zmmul-64.d: New failure test (RV64 + Zmmul but with no M). * testsuite/gas/riscv/m-ext-fail-zmmul-64.l: Likewise. * testsuite/gas/riscv/m-ext-fail-noarch-64.d: New failure test (no Zmmul or M). * testsuite/gas/riscv/m-ext-fail-noarch-64.l: Likewise. include/ * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZMMUL. ld/ * testsuite/ld-riscv-elf/attr-merge-arch-01.d: We don't care zmmul in these testcases, so just replaced m by a. * testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p0.s: Renamed. * testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p1.s: Renamed. opcodes/ * riscv-opc.c (riscv_opcodes): Updated multiply instructions to zmmul.
2022-08-28PR29494 Trailing jump table on ARMAlan Modra1-6/+6
out_inc_line_addr and relax_inc_line_addr are passed INT_MAX as line_delta to flag end of section. This filters its way down to size_inc_line_addr and emit_inc_line_addr. Pass line_delta on to scale_addr_delta where it can be used to omit an unaligned opcode error. PR 29494 * dwarf2dbg.c (scale_addr_delta): Delete unnecessary forward decl. Add line_delta param. Don't print error at end of section, just round the address down. (size_inc_line_addr, emit_inc_line_addr): Adjust calls.
2022-08-25GAS: Add a return type tag to DWARF DIEs generated for function symbols.Nick Clifton6-4/+82
PR 29517 * dwarf2dbg.c (GAS_ABBREV_COMP_UNIT): New defined constant. (GAS_ABBREV_SUBPROG): New defined constant. (GAS_ABBREV_NO_TYPE): New defined constant. (out_debug_abbrev): Use the new defined constants when emitting abbreviation numbers. Generate an abbreviation for an unspecified type. (out_debug_info): Use the new defined constants when referring to abbreviations. Generate a use of the no_type abbreviation. Reference the use when generating DIEs for functions. * testsuite/gas/elf/dwarf-3-func.d: Update to allow for newly extended output from the assembler. * testsuite/gas/elf/dwarf-5-func-global.d: Likewise. * testsuite/gas/elf/dwarf-5-func-local.d: Likewise. * testsuite/gas/elf/dwarf-5-func.d: Likewise.
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