RISC-V: Add T-Head CMO vendor extension

T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the XTheadCmo extension, a collection of T-Head specific
cache management operations.
The 'th' prefix and the "XTheadCmo" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).

In total XTheadCmo introduces the following 21 instructions:

* DCACHE.{C,CI,I}ALL
* DCACHE.{C,CI,I}{PA,VA,SW} rs1
* DCACHE.C{PAL1,VAL1} rs1
* ICACHE.I{ALL,ALLS}
* ICACHE.I{PA,VA} rs1
* L2CACHE.{C,CI,I}ALL

Contrary to Zicbom, the XTheadCmo instructions don't have a constant
displacement, therefore we have a different syntax for the arguments.
To clarify this is intended behaviour, there is a set of negative test
for Zicbom-style arguments in x-thead-cmo-fail.s.

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

v2:
- Add missing DECLARE_INSN() list
- Fix ordering

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

6 files changed, 103 insertions, 0 deletions

diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 30afd20..10e9429 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -704,5 +704,9 @@ extensions supported and provides the location of their
 publicly-released documentation:
 
 @table @r
+@item XTheadCmo
+The XTheadCmo extension provides instructions for cache management.
+
+It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}.
 
 @end table
diff --git a/gas/testsuite/gas/riscv/x-thead-cmo-fail.d b/gas/testsuite/gas/riscv/x-thead-cmo-fail.d
new file mode 100644
index 0000000..de794ea
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-cmo-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64i_xtheadcmo
+#source: x-thead-cmo-fail.s
+#error_output: x-thead-cmo-fail.l
diff --git a/gas/testsuite/gas/riscv/x-thead-cmo-fail.l b/gas/testsuite/gas/riscv/x-thead-cmo-fail.l
new file mode 100644
index 0000000..4381fe1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-cmo-fail.l
@@ -0,0 +1,22 @@
+.*: Assembler messages:
+.*: Error: illegal operands `th.dcache.call x1'
+.*: Error: illegal operands `th.dcache.ciall x1'
+.*: Error: illegal operands `th.dcache.iall x1'
+.*: Error: illegal operands `th.dcache.cpa 0\(x1\)'
+.*: Error: illegal operands `th.dcache.cipa 0\(x1\)'
+.*: Error: illegal operands `th.dcache.ipa 0\(x1\)'
+.*: Error: illegal operands `th.dcache.cva 0\(x1\)'
+.*: Error: illegal operands `th.dcache.civa 0\(x1\)'
+.*: Error: illegal operands `th.dcache.iva 0\(x1\)'
+.*: Error: illegal operands `th.dcache.csw 0\(x1\)'
+.*: Error: illegal operands `th.dcache.cisw 0\(x1\)'
+.*: Error: illegal operands `th.dcache.isw 0\(x1\)'
+.*: Error: illegal operands `th.dcache.cpal1 0\(x1\)'
+.*: Error: illegal operands `th.dcache.cval1 0\(x1\)'
+.*: Error: illegal operands `th.icache.iall x1'
+.*: Error: illegal operands `th.icache.ialls x1'
+.*: Error: illegal operands `th.icache.ipa 0\(x1\)'
+.*: Error: illegal operands `th.icache.iva 0\(x1\)'
+.*: Error: illegal operands `th.l2cache.call x1'
+.*: Error: illegal operands `th.l2cache.ciall x1'
+.*: Error: illegal operands `th.l2cache.iall x1'
diff --git a/gas/testsuite/gas/riscv/x-thead-cmo-fail.s b/gas/testsuite/gas/riscv/x-thead-cmo-fail.s
new file mode 100644
index 0000000..591d982
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-cmo-fail.s
@@ -0,0 +1,22 @@
+target:
+	th.dcache.call	x1
+	th.dcache.ciall	x1
+	th.dcache.iall	x1
+	th.dcache.cpa	0(x1)
+	th.dcache.cipa	0(x1)
+	th.dcache.ipa	0(x1)
+	th.dcache.cva	0(x1)
+	th.dcache.civa	0(x1)
+	th.dcache.iva	0(x1)
+	th.dcache.csw	0(x1)
+	th.dcache.cisw	0(x1)
+	th.dcache.isw	0(x1)
+	th.dcache.cpal1	0(x1)
+	th.dcache.cval1	0(x1)
+	th.icache.iall	x1
+	th.icache.ialls	x1
+	th.icache.ipa	0(x1)
+	th.icache.iva	0(x1)
+	th.l2cache.call	x1
+	th.l2cache.ciall	x1
+	th.l2cache.iall	x1
diff --git a/gas/testsuite/gas/riscv/x-thead-cmo.d b/gas/testsuite/gas/riscv/x-thead-cmo.d
new file mode 100644
index 0000000..f482ddc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-cmo.d
@@ -0,0 +1,30 @@
+#as: -march=rv64i_xtheadcmo
+#source: x-thead-cmo.s
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+0010000b[ 	]+th.dcache.call
+[ 	]+[0-9a-f]+:[ 	]+0030000b[ 	]+th.dcache.ciall
+[ 	]+[0-9a-f]+:[ 	]+0020000b[ 	]+th.dcache.iall
+[ 	]+[0-9a-f]+:[ 	]+0295000b[ 	]+th.dcache.cpa[ 	]+a0
+[ 	]+[0-9a-f]+:[ 	]+02b5800b[ 	]+th.dcache.cipa[ 	]+a1
+[ 	]+[0-9a-f]+:[ 	]+02a6000b[ 	]+th.dcache.ipa[ 	]+a2
+[ 	]+[0-9a-f]+:[ 	]+0256800b[ 	]+th.dcache.cva[ 	]+a3
+[ 	]+[0-9a-f]+:[ 	]+0277000b[ 	]+th.dcache.civa[ 	]+a4
+[ 	]+[0-9a-f]+:[ 	]+0267800b[ 	]+th.dcache.iva[ 	]+a5
+[ 	]+[0-9a-f]+:[ 	]+0218000b[ 	]+th.dcache.csw[ 	]+a6
+[ 	]+[0-9a-f]+:[ 	]+0238800b[ 	]+th.dcache.cisw[ 	]+a7
+[ 	]+[0-9a-f]+:[ 	]+0222800b[ 	]+th.dcache.isw[ 	]+t0
+[ 	]+[0-9a-f]+:[ 	]+0283000b[ 	]+th.dcache.cpal1[ 	]+t1
+[ 	]+[0-9a-f]+:[ 	]+0243800b[ 	]+th.dcache.cval1[ 	]+t2
+[ 	]+[0-9a-f]+:[ 	]+0100000b[ 	]+th.icache.iall
+[ 	]+[0-9a-f]+:[ 	]+0110000b[ 	]+th.icache.ialls
+[ 	]+[0-9a-f]+:[ 	]+038e000b[ 	]+th.icache.ipa[ 	]+t3
+[ 	]+[0-9a-f]+:[ 	]+030e800b[ 	]+th.icache.iva[ 	]+t4
+[ 	]+[0-9a-f]+:[ 	]+0150000b[ 	]+th.l2cache.call
+[ 	]+[0-9a-f]+:[ 	]+0170000b[ 	]+th.l2cache.ciall
+[ 	]+[0-9a-f]+:[ 	]+0160000b[ 	]+th.l2cache.iall
diff --git a/gas/testsuite/gas/riscv/x-thead-cmo.s b/gas/testsuite/gas/riscv/x-thead-cmo.s
new file mode 100644
index 0000000..2a4b54a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-cmo.s
@@ -0,0 +1,22 @@
+target:
+	th.dcache.call
+	th.dcache.ciall
+	th.dcache.iall
+	th.dcache.cpa	a0
+	th.dcache.cipa	a1
+	th.dcache.ipa	a2
+	th.dcache.cva	a3
+	th.dcache.civa	a4
+	th.dcache.iva	a5
+	th.dcache.csw	a6
+	th.dcache.cisw	a7
+	th.dcache.isw	t0
+	th.dcache.cpal1	t1
+	th.dcache.cval1	t2
+	th.icache.iall
+	th.icache.ialls
+	th.icache.ipa	t3
+	th.icache.iva	t4
+	th.l2cache.call
+	th.l2cache.ciall
+	th.l2cache.iall